Intel 253668-032US Manuel D’Utilisation
Vol. 3 15-35
MACHINE-CHECK ARCHITECTURE
Table 15-16 lists values of relevant bit fields of IA32_MCi_STATUS for archi-
tecturally defined SRAO errors.
For both the memory scrubbing and L3 explicit writeback errors, the ADDRV
and MISCV flags in the IA32_MCi_STATUS register are set to indicate that
the offending physical address information is available from the
IA32_MCi_MISC and the IA32_MCi_ADDR registers. For the memory scrub-
bing and L3 explicit writeback errors, the address mode in the
IA32_MCi_MISC register should be set as physical address mode (010b) and
the address LSB information in the IA32_MCi_MISC register should indicate
the lowest valid address bit in the address information provided from the
IA32_MCi_ADDR register.
An MCE signal is broadcast to all logical processors on the system on which
An MCE signal is broadcast to all logical processors on the system on which
the UCR errors are supported. MCi_STATUS banks can be shared by logical
processors within a core or within the same package. So several logical
processors may find an SRAO error in the shared IA32_MCi_STATUS bank
but other processors do not find it in any of the IA32_MCi_STATUS banks.
Table 15-17 shows the RIPV and EIPV flag indication in the
Table 15-15. MCA Compound Error Code Encoding for SRAO Errors
Type
MCACOD Value MCA Error Code Encoding
1
NOTES:
1. Note that for both of these errors the correction report filtering (F) bit (bit 12) of the MCA error is
0, indicating "normal" filtering.
Memory Scrubbing
0xC0 - 0xCF
0000_0000_1100_CCCC
000F 0000 1MMM CCCC (Memory Controller Error), where
Memory subfield MMM = 100B (memory scrubbing)
Channel subfield CCCC = channel # or generic
000F 0000 1MMM CCCC (Memory Controller Error), where
Memory subfield MMM = 100B (memory scrubbing)
Channel subfield CCCC = channel # or generic
L3 Explicit Writeback 0x17A
0000_0001_0111_1010
000F 0001 RRRR TTLL (Cache Hierarchy Error) where
Request subfields RRRR = 0111B (Eviction)
Transaction Type subfields TT = 10B (Generic)
Level subfields LL = 10B
000F 0001 RRRR TTLL (Cache Hierarchy Error) where
Request subfields RRRR = 0111B (Eviction)
Transaction Type subfields TT = 10B (Generic)
Level subfields LL = 10B
Table 15-16. IA32_MCi_STATUS Values for SRAO Errors
SRAO Error
Valid
OVER UC EN MISCV ADDRV PCC S AR MCACOD
Memory Scrubbing
1
0
1
1
1
1
0
1 0
0xC0-0xCF
L3 Explicit Writeback 1
0
1
1
1
1
0
1 0
0x17A