Intel PCI Manuel D’Utilisation
Receive and Transmit Description
Software Developer’s Manual
29
Figure 3-3. Packet Delay Timer Operation (State Diagram)
3.2.7.1.2 Receive Interrupt Absolute Delay Timer (RADV)
The Absolute Timer ensures that a receive interrupt is generated at some predefined interval after
the first packet is received. The absolute timer is started once a packet is received and transferred to
host memory (specifically, after the last packet data byte is written to memory) but is NOT
reinitialized / restarted each time a new packet is received. When the Absolute Timer expires (no
reinitialized / restarted each time a new packet is received. When the Absolute Timer expires (no
receive interrupt has been generated for the amount of time defined in RADV) the Receive Timer
Interrupt is generated.
Setting RADV to 0b or RDTR to 0b disables the Absolute Timer. To disable the Packet Timer only,
RDTR should be set to RADV + 1b.
RDTR should be set to RADV + 1b.
The Absolute Timer is reinitialized (but not started) when the Receive Timer Interrupt is generated
due to a Packet Timer expiration or Small Receive Packet Detect Interrupt.
Running
Packet received &
transferred to host
memory
Packet received &
transferred to host
transferred to host
memory
Generate
Int
Timer expires
Other receive
timer interrupt
Initial State
Idle
Restart Count
Restart Count