Renesas SH7264 Manuel D’Utilisation
Section 14 Realtime Clock
Page 678 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Register Name
Abbreviation
R/W
Initial Value
Address
Access
Size
Size
Date alarm register
RDAYAR
R/W
H'xx
H'FFFE6018
8
Month alarm register
RMONAR R/W
H'xx
H'FFFE601A 8
Year alarm register
RYRAR
R/W
H'xxxx
H'FFFE6020
16
Control register 1
RCR1
R/W
H'xx
H'FFFE601C
8
Control register 2
RCR2 R/W
H'09 H'FFFE601E
8
Control register 3
RCR3 R/W
H'x0 H'FFFE6024
8
Control register 5
RCR5
R/W
H'xx
H'FFFE6026
8
Frequency register H
RFRH R/W
H'xxxx H'FFFE602A
16
Frequency register L
RFRL R/W
H'xxxx H'FFFE602C
16
14.3.1
64-Hz Counter (R64CNT)
R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz.
Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the
control register 1 (RCR1) to 1 so that the carrying and reading 64 Hz counter are performed at the
same time is indicated. In this case, the R64CNT should be read again after writing 0 to the CF bit
in RCR1 since the read value is not valid.
control register 1 (RCR1) to 1 so that the carrying and reading 64 Hz counter are performed at the
same time is indicated. In this case, the R64CNT should be read again after writing 0 to the CF bit
in RCR1 since the read value is not valid.
After the RESET bit or ADJ bit in the control register 2 (RCR2) is set to 1, the divider circuit is
initialized and R64CNT is initialized.
initialized and R64CNT is initialized.
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
0
1
2
3
4
5
6
7
0
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
-
1Hz
2Hz
4Hz
8Hz
16Hz 32Hz 64Hz