Renesas R5S72625 Manuel D’Utilisation
Section 11 Multi-Function Timer Pulse Unit 2
Page 472 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
0 TGFA 0
R/(W)*
1
Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for
flag clearing.
capture or compare match. Only 0 can be written, for
flag clearing.
[Clearing conditions]
When the direct memory access controller is
activated by TGIA interrupt
When 0 is written to TGFA after reading
TGFA = 1*
2
[Setting conditions]
When TCNT = TGRA and TGRA is functioning as
output compare register
When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag.
2. If the next flag is set before TGFA is cleared to 0 after reading TGFA = 1, TGFA
remains 1 even when 0 is written to. In this case, read TGFA = 1 again to clear TGFA to
0.
0.