Renesas R5S72626 Manuel D’Utilisation
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 437 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.3
Register Descriptions
Table 11.3 shows the register configuration. To distinguish registers in each channel, an
underscore and the channel number are added as a suffix to the register name; TCR for channel 0
is expressed as TCR_0.
underscore and the channel number are added as a suffix to the register name; TCR for channel 0
is expressed as TCR_0.
Table 11.3 Register Configuration
Channel Register
Name
Abbreviation
R/W
Initial
value
value
Address
Access
Size
Size
0
Timer control register_0
TCR_0
R/W
H'00
H'FFFE4300 8
Timer mode register_0
TMDR_0
R/W
H'00
H'FFFE4301 8
Timer I/O control register H_0
TIORH_0
R/W
H'00
H'FFFE4302 8
Timer I/O control register L_0
TIORL_0
R/W
H'00
H'FFFE4303 8
Timer interrupt enable
register_0
register_0
TIER_0 R/W
H'00 H'FFFE4304
8
Timer status register_0
TSR_0
R/W
H'C0
H'FFFE4305 8
Timer counter_0
TCNT_0 R/W
H'0000
H'FFFE4306
16
Timer general register A_0
TGRA_0
R/W
H'FFFF
H'FFFE4308 16
Timer general register B_0
TGRB_0
R/W
H'FFFF
H'FFFE430A 16
Timer general register C_0
TGRC_0
R/W
H'FFFF
H'FFFE430C 16
Timer general register D_0
TGRD_0
R/W
H'FFFF
H'FFFE430E 16
Timer general register E_0
TGRE_0
R/W
H'FFFF
H'FFFE4320 16
Timer general register F_0
TGRF_0
R/W
H'FFFF
H'FFFE4322 16
Timer interrupt enable register
2_0
2_0
TIER2_0 R/W
H'00 H'FFFE4324
8
Timer status register 2_0
TSR2_0
R/W
H'C0
H'FFFE4325 8
Timer buffer operation transfer
mode register_0
mode register_0
TBTM_0 R/W
H'00 H'FFFE4326
8
1
Timer control register_1
TCR_1
R/W
H'00
H'FFFE4380 8
Timer mode register_1
TMDR_1
R/W
H'00
H'FFFE4381 8
Timer I/O control register_1
TIOR_1
R/W
H'00
H'FFFE4382 8
Timer interrupt enable
register_1
register_1
TIER_1 R/W
H'00 H'FFFE4384
8
Timer status register_1
TSR_1
R/W
H'C0
H'FFFE4385 8