Renesas SH7262 R5S72620 Manuel D’Utilisation
Section 16 Renesas Serial Peripheral Interface
Page 834 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(c) Sequence Control
The transfer format that is employed in master mode is determined by the sequence control
register (SPSCR), command registers 0 to 3 (SPCMD0 to SPCMD3), the bit rate register (SPBR),
the clock delay register (SPCKD), the slave select negation delay register (SSLND), and the next-
access delay register (SPND).
register (SPSCR), command registers 0 to 3 (SPCMD0 to SPCMD3), the bit rate register (SPBR),
the clock delay register (SPCKD), the slave select negation delay register (SSLND), and the next-
access delay register (SPND).
SPSCR is a register used to determine the sequence configuration for serial transfers that are
executed by this module in master mode. The following items are set in command registers
SPCMD0 to SPCMD3: SSL output signal value, MSB/LSB first, data length, some of the bit rate
settings, RSPCK polarity/phase, whether SPCKD is to be referenced, whether SSLND is to be
referenced, and whether SPND is to be referenced. SPBR holds some of the bit rate settings;
SPCKD, a clock delay value; SSLND, an SSL negation delay; and SPND, a next-access delay
value.
executed by this module in master mode. The following items are set in command registers
SPCMD0 to SPCMD3: SSL output signal value, MSB/LSB first, data length, some of the bit rate
settings, RSPCK polarity/phase, whether SPCKD is to be referenced, whether SSLND is to be
referenced, and whether SPND is to be referenced. SPBR holds some of the bit rate settings;
SPCKD, a clock delay value; SSLND, an SSL negation delay; and SPND, a next-access delay
value.
According to the sequence length that is assigned to SPSCR, this module makes up a sequence
comprised of a part or all of SPCMD0 to SPCMD3. This module contains a pointer to the SPCMD
that makes up the sequence. The value of this pointer can be checked by reading bits SPCP1 and
SPCP0 in the sequence status register (SPSSR). When the SPE bit in the control register (SPCR) is
set to 1 and the function of this module is enabled, this module loads the pointer to the commands
in SPCMD0, and incorporates the SPCMD0 settings into the transfer format at the beginning of
serial transfer. This module increments the pointer each time the next-access delay period for a
data transfer ends. Upon completion of the serial transfer that corresponds to the final command
comprising the sequence, this module sets the pointer in SPCMD0, and in this manner the
sequence is executed repeatedly.
comprised of a part or all of SPCMD0 to SPCMD3. This module contains a pointer to the SPCMD
that makes up the sequence. The value of this pointer can be checked by reading bits SPCP1 and
SPCP0 in the sequence status register (SPSSR). When the SPE bit in the control register (SPCR) is
set to 1 and the function of this module is enabled, this module loads the pointer to the commands
in SPCMD0, and incorporates the SPCMD0 settings into the transfer format at the beginning of
serial transfer. This module increments the pointer each time the next-access delay period for a
data transfer ends. Upon completion of the serial transfer that corresponds to the final command
comprising the sequence, this module sets the pointer in SPCMD0, and in this manner the
sequence is executed repeatedly.
SSL negate delay
= 1 RSPCK
Next-access delay
= 3 RSPCK + 2 B
φ
SCKD, SSLND, and SPND must be
referenced. MSB first, 8 bits,
SSL not retained, base division
ratio = 1 CPOL = 0, CPHA = 0
Sequence determined
Pointer
SPCP1
and SPCP0
SPCP1
and SPCP0
Determine transfer
format
format
Refer to SCKD, SSLND, and SPND (if necessary)
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPSCR
Sequence is formed in
SPCMD0 to SPCMD2
RSPCK delay
= 2 RSPCK
SCKD
SSLND
SPND
H'02
H'01
H'E700
H'00
H'02
Figure 16.15 Determination Procedure of Serial Transfer Mode in Master Mode