Renesas R5S72646 Manuel D’Utilisation
Section 5 Clock Pulse Generator
R01UH0134EJ0400 Rev. 4.00
Page 125 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 5.5
CKOEN[1:0] Settings
Setting Normal
Operation
Release of Bus
Mastership
Mastership
Software Standby
Mode
Mode
Deep Standby Mode
00
Output
Output off (Hi-Z)
Output off (Hi-Z)
Low-level or high-level
output
output
01 Output
Output
Low-level
output Low-level
or
high-level
output
10 Output
Output
Output
(unstable
clock output)
Low-level or high-level
output
output
11
Output off (Hi-Z)
Output off (Hi-Z)
Output off (Hi-Z)
Output off (Hi-Z)
5.5
Changing the Frequency
The frequency of the CPU clock (I
) and peripheral clock (P) can be changed by changing the
division rate of divider. The division rate can be changed by software through the frequency
control register (FRQCR).
control register (FRQCR).
5.5.1
Changing the Division Ratio
The division rate of divider can be changed by the following operation.
1. In the initial state, IFC1 to IFC0
B'01 or B'10 and PFC2 to PFC0 B'100 or B'011.
2. Set the desired value in the IFC1 to IFC0 and PFC2 to PFC0 bits. The values that can be set
are limited by the clock operating mode and the multiplication rate of PLL circuit. Note that if
the wrong value is set, this LSI will malfunction.
the wrong value is set, this LSI will malfunction.
3. After the register bits (IFC1 to IFC0 and PFC2 to PFC0) have been set, the clock is supplied of
the new division ratio.
Note: When executing the SLEEP instruction after the frequency has been changed, be sure to
read the frequency control register (FRQCR) three times before executing the SLEEP
instruction.
instruction.