Intel Xeon E7420 AD80583QH0468M Fiche De Données
Codes de produits
AD80583QH0468M
Introduction
10
Intel® Xeon® Processor 7400 Series Datasheet
Intel® Xeon® Processor 7400 Series are intended for high performance multi-
processor server systems. The processors support a Multiple Independent Bus (MIB)
architecture with one processor on each bus. The MIB architecture provides improved
performance by allowing increased FSB speeds and bandwidth. All versions of the
Intel® Xeon® Processor 7400 Series will include manageability features. Components
of the manageability features include an OEM EEPROM and Processor Information ROM
which are accessed through an SMBus interface and contain information relevant to the
particular processor and system in which it is installed. The Intel® Xeon® Processor
7400 Series is packaged in a 604-pin Flip Chip Micro Pin Grid Array (FC-mPGA8)
package and utilizes a surface-mount Zero Insertion Force (ZIF) mPGA604 socket. The
Intel® Xeon® Processor 7400 Series supports 40-bit addressing.
processor server systems. The processors support a Multiple Independent Bus (MIB)
architecture with one processor on each bus. The MIB architecture provides improved
performance by allowing increased FSB speeds and bandwidth. All versions of the
Intel® Xeon® Processor 7400 Series will include manageability features. Components
of the manageability features include an OEM EEPROM and Processor Information ROM
which are accessed through an SMBus interface and contain information relevant to the
particular processor and system in which it is installed. The Intel® Xeon® Processor
7400 Series is packaged in a 604-pin Flip Chip Micro Pin Grid Array (FC-mPGA8)
package and utilizes a surface-mount Zero Insertion Force (ZIF) mPGA604 socket. The
Intel® Xeon® Processor 7400 Series supports 40-bit addressing.
Notes:
1.
Total accessible size of the L3 cache may vary by up to thirty-two (32) cache lines (64 bytes per line),
depending on usage and operating environment.
2.
Total accessible size of L2 caches may vary by one cache line pair (128 bytes) per core, depending on
usage and operating environment
Intel® Xeon® Processor 7400 Series-based platforms implement independent core
voltage (V
voltage (V
CC
) power planes for each processor. FSB termination voltage (V
TT
) is shared
and must connect to all FSB agents. The processor core voltage utilizes power delivery
guidelines specified by VRM/EVRD 11.0 and its associated load line (see Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for further details). VRM/EVRD 11.0 will support the power requirements of
all frequencies of the processors including Flexible Motherboard Guidelines (FMB) (see
guidelines specified by VRM/EVRD 11.0 and its associated load line (see Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for further details). VRM/EVRD 11.0 will support the power requirements of
all frequencies of the processors including Flexible Motherboard Guidelines (FMB) (see
). Refer to the appropriate platform design guidelines for implementation
details.
The Intel® Xeon® Processor 7400 Series supports 1066 MTS (Mega Transfers per
Second) Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply
protocol and Source-Synchronous Transfer (SST) of address and data to improve
performance. The processor transfers data four times per bus clock (4X data transfer
rate). Along with the 4X data bus, the address bus can deliver addresses two times per
bus clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 8.5 GBytes per second. The FSB is
also used to deliver interrupts.
Second) Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply
protocol and Source-Synchronous Transfer (SST) of address and data to improve
performance. The processor transfers data four times per bus clock (4X data transfer
rate). Along with the 4X data bus, the address bus can deliver addresses two times per
bus clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 8.5 GBytes per second. The FSB is
also used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
details are fully described in the appropriate platform design guidelines (refer to
).
The Intel® Xeon® Processor 7400 Series supports Intel
®
Cache Safe Technology on
the L3 cache. This provides a threshold-based mechanism for cache error reporting.
Intel recommends that fault prediction handlers rely on this mechanism to assess
processor cache health. Please refer to the Intel
Intel recommends that fault prediction handlers rely on this mechanism to assess
processor cache health. Please refer to the Intel
®
64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A for more detailed information.
Table 1-1.
Processor Features
# of Processor
Cores
L1 Cache per
Core
Total L2 Advanced
Transfer Cache
Total L3 Shared
Front Side Bus
Transfer Rate
Package
4 or 6
32 KB
instruction
32 KB data
6M or 9M
Shared L2 Cache
12M or 16M
1066 MTS
FC-mPGA8