TallyGenicom 2440 Mode D'Emploi

B-4

Nibble mode

10

PtrClk 
(nACK)

Output

Reverse data transfer phase:This signal 
goes high when data being sent to the 
host is established. 
Reverse idle phase: This signal is set low 
then goes high to interrupt the host, indi-
cating that data is available.

11

PtrBusy 
(BUSY)

Output

Reverse data transfer phase: Data bit 3, 
data bit 7, then forward path (host to 
printer) busy status.

12

AckDataReq 
(PE)

Output

Reverse data transfer phase: Data bit 2, 
then data bit 6.
Reverse idle phase: This signal is set high 
until the host requests data and, after that, 
follows the Data Available signal.

13

Xflag 
(SELECT)

Output

Reverse data transfer phase: Data bit 1 
then 5.

14

HostBusy 
(nAUTO-
FEED)

Input

Reverse data transfer phase: This signal is 
set low when the host can receive data, 
and goes high when the host has received 
data.  Following a reverse data transfer, 
the interface enters the reverse idle phase 
when the HostBusy signal goes low and 
the printer has no data.
Reverse idle phase: This signal goes high 
when the Printer Clock signal goes low so 
that the interface re-enters the reverse 
data transfer phase.  If it goes high with 
the 1284 Active signal low, the 1284 idle 
phase is aborted and the interface returns 
to the compatibility mode.

32

nDataAvail 
(nERROR)

Output

Reverse data transfer phase: This signal is 
set low when the printer is ready to send 
data to the host.  During the data transfer, 
it is used as data bit 0 (LSB), then data bit 
4.
Reverse idle phase: This signal is used to 
indicate that data is available.