Intel Pentium 4 RK80532PE056512 Manuel D’Utilisation
Codes de produits
RK80532PE056512
Intel
®
Pentium
®
4 Processor in the 423-pin Package
69
SMI#
Input
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, the processor saves the current
state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
On accepting a System Management Interrupt, the processor saves the current
state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
If SMI# is asserted during the deassertion of RESET# the processor will tristate its
outputs.
outputs.
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the system
bus and APIC units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the system
bus and APIC units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
as the Test Access Port).
TDI
Input
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
serial input needed for JTAG specification support.
TDO
Output
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
the serial output needed for JTAG specification support.
TESTHI[10:0]
Input
TESTHI[10:0] must be connected to a V
CC
power source through 1-10 k
Ω
resistors
for proper processor operation. See Section 2.5 for more details.
THERMDA
Other
Thermal Diode Anode. See Section 7.3.1.
THERMDC
Other
Thermal Diode Cathode. See Section 7.3.1.
THERMTRIP#
Output
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135°C. This is signalled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active. There is no
hysteresis built into the thermal sensor itself; as long as the die temperature drops
below the trip level, a RESET# pulse will reset the processor and execution will
continue. If the temperature has not dropped below the trip level, the processor will
continue to drive THERMTRIP# and remain stopped.
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135°C. This is signalled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active. There is no
hysteresis built into the thermal sensor itself; as long as the die temperature drops
below the trip level, a RESET# pulse will reset the processor and execution will
continue. If the temperature has not dropped below the trip level, the processor will
continue to drive THERMTRIP# and remain stopped.
TMS
Input
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
tools.
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all system bus agents.
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all system bus agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset. This can be done with a 680
low during power on Reset. This can be done with a 680
Ω
pull-down resistor.
V
CCA
Input
V
CCA
provides isolated power for the internal processor core PLL’s. Refer to the
Intel
®
Pentium
®
4 Processor and Intel
®
850 Chipset Platform Design Guide for
complete implementation details.
V
CCIOPLL
Input
V
CCIOPLL
provides isolated power for internal processor system bus PLL’s. Follow the
guidelines for V
CCA
, and refer to the Intel
®
Pentium
®
4 Processor and Intel
®
850
Chipset Platform Design Guide for complete implementation details.
V
CCSENSE
Output
V
CCSENSE
is an isolated low impedance connection to processor core power (V
CC
). It
can be used to sense or measure power near the silicon with little noise.
Table 32. Signal Description (Page 7 of 8)
Name
Type
Description