Intel Xeon X3460 BX80605X3460 Manuel D’Utilisation
Codes de produits
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
215
Processor Uncore Configuration Registers
6
RW
0
DIVBY3EN
Divide By 3 enable. When set, MAD would use the longer pipeline for
Divide By 3 enable. When set, MAD would use the longer pipeline for
transactions that are 3- or 6-way interleaved and shorter pipeline for all
other transactions. The SAG registers must be appropriately programmed
as well.
5
RO
0
Reserved
4
RW
0
CHANNELRESET1
Reset only the state within the channel. Equivalent to pulling warm reset
Reset only the state within the channel. Equivalent to pulling warm reset
for that channel.
3
RW
0
CHANNELRESET0
Reset only the state within the channel. Equivalent to pulling warm reset
Reset only the state within the channel. Equivalent to pulling warm reset
for that channel.
2
RW
0
AUTOPRECHARGE
Autoprecharge enable. This bit should be set with the closed page bit. If it
Autoprecharge enable. This bit should be set with the closed page bit. If it
is not set with closed page, address decode will be done without setting
the autoprecharge bit.
1
RW
0
ECCEN. ECC Checking enables. When this bit is set in lockstep mode the
ECC checking is for the x8 SDDC. ECCEN without Lockstep enables the x4
SDDC ECC checking.
0
RW
0
CLOSED_PAGE
When set, the MC supports a Closed Page policy. The default is Open Page
When set, the MC supports a Closed Page policy. The default is Open Page
but BIOS should always configure this bit.
Device:
3
Function: 0
Offset:
48h
Access as a DWord