Intel AT80604005280AA Manuel D’Utilisation
Intel® Xeon® Processor 7500 Datasheet, Volume 1
51
Electrical Specifications
Figure 2-16. FLASHROM Timing Waveform
Table 2-31.TAP Signal Group AC Timing Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes
1,2
Notes:
1. Not 100% tested. These parameters are based on design characterization.
2. It is recommended that TMS be asserted while TRST_N is being deasserted.
Transmitter and Receiver Timings
F
TAP
TCK Frequency
66
MHz
3
3. This specification is based on the capabilities of the ITP-XDP debug port tool, not on processor silicon.
T
p
TCK Period
15
ns
T
S
TDI, TMS Setup Time
7.5
ns
4,5
4. Referenced to the rising edge of TCK.
5. Specification for a minimum swing defined between TAP V
T-
to V
T+
. This assumes a minimum edge rate of 0.5
V/ns.
T
H
TDI, TMS Hold Time
7.5
ns
T
X
TDO Clock to Output Delay
7.5
24
ns
6
6. Referenced to the falling edge of TCK.
TRST_N Assert Time
30
ns
7
7. TRST_N must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
Figure 2-17. TAP Valid Delay Timing Waveform
t
DELAY
t
SETUP
t
HOLD
t
CS_DE
t
CS_AS
FLASHROM_CS
FLASHROM_CLK
FLASHROM_DATO
FLASHROM_DATI
Tx = TDO Clock to Output Delay
Ts = TDI, TMS Setup Time
Th = TDI, TMS Hold Time
Ts = TDI, TMS Setup Time
Th = TDI, TMS Hold Time
V = 0.5 * VIO
TCK
Signal
Tx
Ts
Th
V
Valid
V
Tp
Tp = TAP Frequency