Intel Xeon L3406 CM80616005010AA Manuel D’Utilisation
Codes de produits
CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
178
Datasheet, Volume 2
3.7.1.5
QPI[0]LCRDC—Intel
®
QuickPath Interconnect Link Credit Control
Registers controls what credits are defined for each message class on VN0 and VNA.
These credits are made visible on Intel QuickPath Interconnect during the initialization
phase of the link layer. Incorrect programming can result in overflow of the receive
queue. When returning credits on Intel QuickPath Interconnect this register is used in
conjunction with the Intel QuickPath Interconnect standard register QPI[0]LCL—Intel
QuickPath Interconnect Link Control to determine how many credits are returned.
These credits are made visible on Intel QuickPath Interconnect during the initialization
phase of the link layer. Incorrect programming can result in overflow of the receive
queue. When returning credits on Intel QuickPath Interconnect this register is used in
conjunction with the Intel QuickPath Interconnect standard register QPI[0]LCL—Intel
QuickPath Interconnect Link Control to determine how many credits are returned.
This value is captured and used by the Link Layer when exiting the parameter
exchange. This state is referred to as “Begin Normal Operation.”
exchange. This state is referred to as “Begin Normal Operation.”
Register: QPI[0]LCRDC
Device:
16
Function:
0
Offset: F8h
Bit
Attr
Default
Description
31
RV
0
Reserved
30:28
RV
0h
Reserved
27
RV
0
Reserved
26:24
RWDS
1/2h
VN0 - NCB credits
Allowed values = 0–7 credits
Allowed values = 0–7 credits
23
RV
0
Reserved
22:20
RWDS
1/2h
VN0 - NCS credits
Allowed values = 0–7 credits
Allowed values = 0–7 credits
19
RV
0
Reserved
18:16
RWDS
1/2h
VN0 - NDR credits
With Isoc enabled this value is expected to be set at 3 to ensure QoS with
With Isoc enabled this value is expected to be set at 3 to ensure QoS with
processor.
Allowed values = 0–7 credits
Allowed values = 0–7 credits
15
RV
0
Reserved
14:12
RWDS
1/2h
VN0 - DRS credits
With Isoc enabled this value is expected to be set at 4 to ensure QoS with
With Isoc enabled this value is expected to be set at 4 to ensure QoS with
processor.
Allowed values = 0–7 credits
Allowed values = 0–7 credits
11
RV
0
Reserved
10:8
RWDS
0/2h
VN0 - Snp credits
Allowed values = 0–7 credits
Snp credits are only needed for debug mode only. This should be set to 0 for
Allowed values = 0–7 credits
Snp credits are only needed for debug mode only. This should be set to 0 for
normal operation. It can be changed to 1 for debug mode.
7
RV
0
Reserved
6:0
RWDS
66/4Ah
VNA credits
Default is set to 102 (66h), which allows for 1 VN0 credit per message class
Default is set to 102 (66h), which allows for 1 VN0 credit per message class
to be assigned with standard headers.
0 –127 credits
Additional modifiers on VNA credits.
If VN0 Snp Credits is set to 1, this must be set to one less credit.
If VN0 DRS credits are set to the recommended isoc value (4), this should be
0 –127 credits
Additional modifiers on VNA credits.
If VN0 Snp Credits is set to 1, this must be set to one less credit.
If VN0 DRS credits are set to the recommended isoc value (4), this should be
set to 33 less credits.