Intel Xeon L3406 CM80616005010AA Manuel D’Utilisation

Datasheet, Volume 2

81

63:50

RO

0

49

RW1CS

0

Reserved

48

RW1C

0

Received PME_TO_ACK
Indicates that Integrated I/O received a PME turn off ACK packet or it 

timed out waiting for the packet.

47:38

RO

0

Reserved

37

RV

0

Reserved

36

RWS

0

Form-Factor
Indicates what form-factor a particular root port controls
0 = CEM/Cable

1 = SIOM
This bit is used to interpret bit 6 in the VPP serial stream for the port as 

either MRL# (CEM/Cable) input or EMLSTS# (SIOM) input. 

35

RW

0

Override System Error on PCI Express Fatal Error Enable
When set, fatal errors on PCI Express (that have been successfully 

propagated to the primary interface of the port) are sent to the Integrated 

I/O core error logic (for further escalation) regardless of the setting of the 

equivalent bit in the ROOTCON register. When clear, the fatal errors are 

only propagated to the Integrated I/O core error logic if the equivalent bit 

in ROOTCTRL register is set.

34

RW

0

Override System Error on PCI Express Non-Fatal Error Enable 

When set, non-fatal errors on PCI Express (that have been successfully 

propagated to the primary interface of the port) are sent to the Integrated 

I/O core error logic (for further escalation) regardless of the setting of the 

equivalent bit in the ROOTCON register. When clear, the non-fatal errors 

are only propagated to the Integrated I/O core error logic if the equivalent 

bit in ROOTCON register is set.

33

RW

0

Override System Error on PCI Express Correctable Error Enable 

When set, correctable errors on PCI Express (that have been successfully 

propagated to the primary interface of the port) are sent to the Integrated 

I/O core error logic (for further escalation) regardless of the setting of the 

equivalent bit in the ROOTCON register. When clear, the correctable errors 

are only propagated to the Integrated I/O core error logic if the equivalent 

bit in ROOTCON register is set.

32

RW

0

ACPI PME Interrupt Enable
When set, Assert/Deassert_PMEGPE messages are enabled to be 

generated when ACPI mode is enabled for handling PME messages from 

PCI Express. When this bit is cleared (from a 1), a Deassert_PMEGPE 

message is scheduled on behalf of the root port if an Assert_PMEGPE 

message was sent earlier from the root port.

31

RW

0

Disable L0s on Transmitter
When set, Integrated I/O never puts its tx in L0s state, even if OS enables 

it using the Link Control register.

30

RV

0

Reserved

29

RW

1

cfg_to_en 
Disables/enables configuration timeouts, independently of other timeouts.

28

RO

0