Intel 7140N LF80550KF093007 Fiche De Données
Codes de produits
LF80550KF093007
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
71
Signal Definitions
SMI#
I
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
On the Dual-Core Intel Xeon processor 7100 series, it is required that SMI#
On the Dual-Core Intel Xeon processor 7100 series, it is required that SMI#
assertion be observed 8 BCLKs before the Response Status (RS[2:0]#) is
observed by the processor.
If SMI# is asserted during the deassertion of RESET#, the processor will tri-
If SMI# is asserted during the deassertion of RESET#, the processor will tri-
state its outputs.
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction,
and stops providing internal clock signals to all processor core units except the
front side bus and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Access Port.
TDI
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TEST_BUS
I
Must be connected to all other processor TEST_BUS signals in the system. See
the appropriate platform design guideline for termination details.
TESTHI[6:0]
I
TESTHI[6:0] must be connected to a V
TT
power source through a resistor for
proper processor operation. See
for more details.
THERMTRIP#
O
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a temperature beyond which permanent silicon
damage may occur. THERMTRIP# (Thermal Trip) will activate at a temperature
that is approximately 15°C above the maximum case temperature (TC).
Measurement of the temperature is accomplished through an internal thermal
sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal
clocks (thus halting program execution) in an attempt to reduce the processor
junction temperature. To protect the processor its core voltage (VCC) must be
removed following the assertion of THERMTRIP#. Driving of the THERMTRIP#
signals is enabled within 10 µs of the assertion of PWRGOOD and is disabled on
de-assertion of PWRGOOD. Once activated, THERMTRIP# remains latched until
PWRGOOD is de-asserted. While the deassertion of the PWRGOOD signal will
de-assert THERMTRIP#, if the processor’s junction temperature remains at or
above the trip level, THERMTRIP# will again be asserted within 10 µs of the
assertion of PWRGOOD. Thermtrip should not be sampled until 10 µs after
PWRGOOD assertion at the processor.
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRDY#
I
TRDY# (Target Ready) is asserted by the target (chipset) to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must
connect the appropriate pins of all front side bus agents.
TRST#
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven electrically low during power on Reset. Please refer to the eXtended
Debug Port: Debug Port Design Guide for Twin Castle Chipset Platforms or the
eXtended Debug Port: Debug Port Design Guide for MP Platforms for details.
V
CACHE
I
V
CACHE
provides power to the L3 cache on the Dual-Core Intel Xeon processor
7100 series.
V
CC
I
V
CC
provides power to the core logic of the Dual-Core Intel Xeon processor
7100 series.
V
CCA
I
V
CCA
provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power. Refer to the appropriate platform
design guide for complete implementation details.
Table 5-1.
Signal Definitions (Sheet 7 of 8)
Name
Type
Description