Intel QX9775 EU80574XL088N Fiche De Données
Codes de produits
EU80574XL088N
Land Listing and Signal Description
66
Datasheet
BPM5#
BPM4#
BPM3#
BPM[2:1]#
BPM0#
BPM4#
BPM3#
BPM[2:1]#
BPM0#
I/O
O
I/O
O
I/O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and
performance monitor signals. They are outputs from the
processor which indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate
pins of all FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for
the TAP port. PRDY# is a processor output used by debug
tools to determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for
the TAP port. PREQ# is used by debug tools to request
debug operation of the processors.
BPM[5:4]# must be bussed to all bus agents.
performance monitor signals. They are outputs from the
processor which indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate
pins of all FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for
the TAP port. PRDY# is a processor output used by debug
tools to determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for
the TAP port. PREQ# is used by debug tools to request
debug operation of the processors.
BPM[5:4]# must be bussed to all bus agents.
2
BPMb3#
BPMb[2:1]#
BPMb0#
BPMb[2:1]#
BPMb0#
I/O
O
I/O
BPMb[3:0]# (Breakpoint Monitor) are breakpoint and
performance monitor signals. They are outputs from the
processor which indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. BPMb[3:0]# should connect the appropriate
pins of all FSB agents.
performance monitor signals. They are outputs from the
processor which indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. BPMb[3:0]# should connect the appropriate
pins of all FSB agents.
BPRI#
I
BPRI# (Bus Priority Request) is used to arbitrate for
ownership of the processor FSB. It must connect the
appropriate pins of all processor FSB agents. Observing
BPRI# active (as asserted by the priority agent) causes
all other agents to stop issuing new requests, unless such
requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by
deasserting BPRI#.
ownership of the processor FSB. It must connect the
appropriate pins of all processor FSB agents. Observing
BPRI# active (as asserted by the priority agent) causes
all other agents to stop issuing new requests, unless such
requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by
deasserting BPRI#.
3
BR[1:0]#
I/O
The BR[1:0]# signals are sampled on the active-to-
inactive transition of RESET#. The signal which the agent
samples asserted determines its agent ID. BR0# drives
the BREQ0# signal in the system and is used by the
processor to request the bus.
These signals do not have on-die termination and must be
terminated.
inactive transition of RESET#. The signal which the agent
samples asserted determines its agent ID. BR0# drives
the BREQ0# signal in the system and is used by the
processor to request the bus.
These signals do not have on-die termination and must be
terminated.
3
BSEL[2:0]
O
The BCLK[1:0] frequency select signals BSEL[2:0] are
used to select the processor input clock frequency.
used to select the processor input clock frequency.
and the frequency associated with each combination. The
required frequency is determined by the processors,
chipset, and clock synthesizer. All FSB agents must
operate at the same frequency.
required frequency is determined by the processors,
chipset, and clock synthesizer. All FSB agents must
operate at the same frequency.
COMP[3:0]
I
COMP[3:0] must be terminated to VSS on the baseboard
using precision resistors. These inputs configure the
AGTL+ drivers of the processor.
using precision resistors. These inputs configure the
AGTL+ drivers of the processor.
Table 4-1.
Signal Definitions (Sheet 3 of 11)
Name
Type
Description
Notes