Intel LF80550KG0804M Fiche De Données

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

29

1.

These voltages and frequencies are targets only. A variable voltage source should exist on systems in the event that a 

different voltage is required. See 

 and 

 for more information. 

2.

The voltage specification requirements are measured across the V

CCSENSE

 and V

SSSENSE

 pins using an oscilloscope set to a 

100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 MΩ minimum impedance at the processor socket. 

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not 

coupled into the scope probe. 

3.

Refer to 

 for the minimum, typical, and maximum V

CC

 allowed for a given current. The processor should not be 

subjected to any V

CC

 and I

CC 

combination wherein V

CC 

exceeds V

CC_MAX

 for a given current.

4.

Moreover, V

CC

 should never exceed the VID voltage. Failure to adhere to this specification can shorten the processor lifetime.

5.

V

CC_MIN

 and V

CC_MAX 

are defined at the frequency’s associated I

CC_MAX 

on the V

CC 

load line.

6.

The current specified is also for the HALT State.

7.

FMB is the Flexible Motherboard guideline. These guidelines are for estimation purposes only. See 

 for further 

details on FMB guidelines.

8.

The maximum instantaneous current the processor will draw while the thermal control circuit (TCC) is active as indicated by 

the assertion of PROCHOT# is the same as the maximum I

CC

 for the processor.

9.

The core and cache portions of Stop-Grant current is specified at V

CC

 and V

CACHE

max.

10. Icc_Max specification is based on Vcc Maximum loadline. Refer to 

 for details 

11. These parameters are based on design characterization and are not tested.

12. V

TT 

must be provided via a separate voltage source and must not be connected to V

CC

.

13. These specifications are measured at the package pin.

14. Baseboard bandwidth is limited to 20 MHz.

15. This specification refers to a single processor with R

TT

 enabled.

16. This specification refers to a single processor with R

TT

 disabled.

17. The voltage specification requirements are measured across the V

CC_CACHE_SENSE

 and V

SS_CACHE_SENSE

 pins at the socket with 

a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length 

of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the scope 

probe.

18. This specification represents the V

CC

 reduction due to each VID transition. See 

19. This specification refers to the total reduction of the load line due to VID transitions below the specified VID.

20. I

CC_TDC

 is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for 

the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and 

asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design guidelines for 

further details. The processor is capable of drawing I

CC_TDC

 indefinitely. Refer to 

 for further details on the average 

processor current draw over various time durations. This parameter is based on design characterization and is not tested.

21. I

CACHE_TDC

 is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used 

for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and 

asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design guidelines for 

further details. The processor is capable of drawing I

CACHE_TDC

 indefinitely. This parameter is based on design characterization 

and is not tested.

I

CACHE_TDC

Cache Thermal Design 

Current (TDC)

All freq

35

A

I

TT

FSB termination current

All freq.

4

A

11,15

I

TT

FSB mid-agent current

All freq.

1.3

A

11,16

I

SM_VCC

I

CC

 for SMBus supply

All freq.

100

122.5

mA

11

I

SGnt_CORE

I

CC

 Stop-Grant Core

All freq.

70

A

6,9

I

SGnt_CACHE

I

CC

 Stop-Grant Cache

All freq.

35

A

6,9

I

TCC

I

CC

 TCC active

All freq.

I

CC

A

8

I

CC VCCA

I

CC

 for PLL pin

All freq.

60

mA

I

CC VCCIOPLL

I

CC

 for I/O PLL pin

All freq.

60

mA

I

CC VCCA_CACHE

I

CC

 for L3 cache PLL pin

All freq.

60

mA

I

CC GTLREF

I

CC

 per GTLREF pin

All freq.

200

µA