Epson S1C63000 Manuel D’Utilisation
62
EPSON
S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
ADC %r,[%ir]
Add with carry location [ir reg.] to r reg.
1 cycle
Function:
r
←
r + [ir] + C
Adds the content of the data memory addressed by the ir register (X or Y) and carry (C) to the r
register (A or B).
register (A or B).
Code:
Mnemonic
MSB
LSB
ADC %A,[%X]
1
1
0
0
1
1
1
1
0
0
0
0
0
19E0H
ADC %A,[%Y]
1
1
0
0
1
1
1
1
0
0
0
1
0
19E2H
ADC %B,[%X]
1
1
0
0
1
1
1
1
0
0
1
0
0
19E4H
ADC %B,[%Y]
1
1
0
0
1
1
1
1
0
0
1
1
0
19E6H
Flags:
E
I
C
Z
↓
–
↕
↕
Mode:
Src: Register indirect
Dst: Register direct
Extended addressing: Valid
Dst: Register direct
Extended addressing: Valid
Extended
LDB
%EXT,imm8
operation:
ADC
%r,[%X]
r
←
r + [00imm8] + C (00imm8 = 0000H + 00H to FFH)
LDB
%EXT,imm8
ADC
%r,[%Y]
r
←
r + [FFimm8] + C (FFimm8 = FF00H + 00H to FFH)
ADC %r,[%ir]+
Add with carry location [ir reg.] to r reg. and increment ir reg.
1 cycle
Function:
r
←
r + [ir] + C, ir
←
ir + 1
Adds the content of the data memory addressed by the ir register (X or Y) and carry (C) to the r
register (A or B). Then increments the ir register (X or Y). The flags change due to the operation
result of the r register and the increment result of the ir register does not affect the flags.
register (A or B). Then increments the ir register (X or Y). The flags change due to the operation
result of the r register and the increment result of the ir register does not affect the flags.
Code:
Mnemonic
MSB
LSB
ADC %A,[%X]+
1
1
0
0
1
1
1
1
0
0
0
0
1
19E1H
ADC %A,[%Y]+
1
1
0
0
1
1
1
1
0
0
0
1
1
19E3H
ADC %B,[%X]+
1
1
0
0
1
1
1
1
0
0
1
0
1
19E5H
ADC %B,[%Y]+
1
1
0
0
1
1
1
1
0
0
1
1
1
19E7H
Flags:
E
I
C
Z
↓
–
↕
↕
Mode:
Src: Register indirect
Dst: Register direct
Extended addressing: Invalid
Dst: Register direct
Extended addressing: Invalid