Intel 41210 Manuel D’Utilisation
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
101
Register Description
12.2.46
Offset DAh: PX_SSTS—PCI-X Secondary Status
This is the PCI-X status register for the bridge secondary side.
Table 80.
Offset DAh: PX_SSTS—PCI-X Secondary Status
Bits
Type
Reset
Description
15:9
RO
00h
Reserved
8:6
RO
See
Secondary Clock Frequency (SCF):
This field is set with the frequency of the secondary
bus. The values are as follows:
The default value for this register is given in
5
RO
0b
Split Request Delayed. (SRD):
Ordinarily, this bit is set when the bridge cannot forward a
transaction on the secondary bus to the primary bus because there is not enough room
within the limit specified in the Split Transaction Commitment Limit field in the Downstream
Split Transaction Control Register.
within the limit specified in the Split Transaction Commitment Limit field in the Downstream
Split Transaction Control Register.
The Intel
®
41210 Serial to Parallel PCI Bridge never sets this bit.
4
RO
0b
Split Completion Overrun (SCO):
Ordinarily, this bit is set when a bridge terminates a Split
Completion on the secondary bus with retry or disconnect at next ADB because its buffers
are full.
are full.
The 41210 never sets this bit.
3
RWC
0b
Unexpected Split Completion (USC):
This bit is set when an unexpected split completion
is received with a bus number that matches the 41210 primary bus number but with a
requester ID:tag that does not match any outstanding requests. This bit is cleared by the
software writing a 1.
requester ID:tag that does not match any outstanding requests. This bit is cleared by the
software writing a 1.
2
RWC
0b
Split Completion Discarded (SCD):
This bit is set when the 41210 discards a split
completion moving toward the secondary bus because the requester does not accept it
.
This bit is cleared by the software writing a 1.
1
RO
1b
133 MHz Capable (C133):
This bit indicates that the 41210 secondary interface is capable
of 133 MHz operation in PCI-X mode.
0
RO
1b
64-bit Device (D64):
This bit indicates that the width of the secondary bus is 64 bits.
Bits
Maximum Frequency
Clock Period
000
PCI mode
–
001
66 MHz
15
010
100 MHz
10
011
133 MHz
7.5
1xx
Reserved
Reserved