Daewoo 20q1 Manuel D’Utilisation
DW5255M*(Micro-controller & West/East Teletext Decoder)
DW5255RM*(Micro-controller & Cyrillic Teletext Decoder)
=SDA5255-A*** (SIEMENS Type No.)
DW5255RM*(Micro-controller & Cyrillic Teletext Decoder)
=SDA5255-A*** (SIEMENS Type No.)
(1) General Description
The TDA5255 contains a slicer for VPS and TTX, an accelerating acquisition hardware module, a display
generator for “LEVEL 1” TTX data and a 8 bit u-controller running at 333 nsec cycle time.
The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX
acquisition , transfers data to/from the external memory interface and receives/transmits data via I2C and
UART user interfaces.
The Slicer combined with dedicated hardware stores TTX data in a VBI 1Kbyte buffer.
The u-controller firmware does the total acquisition task (hamming- and parity -checks,
page search and evaluation of header control bits) once per field.
generator for “LEVEL 1” TTX data and a 8 bit u-controller running at 333 nsec cycle time.
The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX
acquisition , transfers data to/from the external memory interface and receives/transmits data via I2C and
UART user interfaces.
The Slicer combined with dedicated hardware stores TTX data in a VBI 1Kbyte buffer.
The u-controller firmware does the total acquisition task (hamming- and parity -checks,
page search and evaluation of header control bits) once per field.
(2) Feature
• Acquisition:
- feature selection via special function register
- simultaneous reception of TTX and VPS
- fixed framing code for VPS and TTX
- programmable framing code window for TTX
- Acquisition during VBI
- direct access to VBI RAM buffer
- Acquisition of packets x/26, x/27, 8/30 (firmware)
- assistance of all relevant checks (firmware)
- 1-bit framing-code error tolerance (switchable)
- simultaneous reception of TTX and VPS
- fixed framing code for VPS and TTX
- programmable framing code window for TTX
- Acquisition during VBI
- direct access to VBI RAM buffer
- Acquisition of packets x/26, x/27, 8/30 (firmware)
- assistance of all relevant checks (firmware)
- 1-bit framing-code error tolerance (switchable)
• Display:
- features selectable via special function register
- 50/60 Hz display
- level 1 serial attribute display pages
- blanking and contrast reduction output
- 8 direct addressable display pages
- 12 x 10 character matrix
- 96 character ROM (standard G0 character set)
- 143 national option characters for 11 languages
- 288 characters for X/26 display
- 64 block mosaic graphic characters
- 32 free addressable characters for OSD in expanded character ROM + 32 inside OSD box
- double height (TOP/BOTTOM)
- conceal/reveal
- transparent foreground/background -inside/outside of a box
- cursor (colour changes from foreground to background colour)
- flash (flash rate 1s)
- programmable horizontal und vertical sync delay
- hardware assisted fast display page erase
- full screen background colour in outer screen
- 50/60 Hz display
- level 1 serial attribute display pages
- blanking and contrast reduction output
- 8 direct addressable display pages
- 12 x 10 character matrix
- 96 character ROM (standard G0 character set)
- 143 national option characters for 11 languages
- 288 characters for X/26 display
- 64 block mosaic graphic characters
- 32 free addressable characters for OSD in expanded character ROM + 32 inside OSD box
- double height (TOP/BOTTOM)
- conceal/reveal
- transparent foreground/background -inside/outside of a box
- cursor (colour changes from foreground to background colour)
- flash (flash rate 1s)
- programmable horizontal und vertical sync delay
- hardware assisted fast display page erase
- full screen background colour in outer screen
• Synchronization:
display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with startstop-oscillator or
display synchronization to sandcastle or Horizontal Sync and Vertical Sync with external clock
independent clock systems for acquisition, display and controller
display synchronization to sandcastle or Horizontal Sync and Vertical Sync with external clock
independent clock systems for acquisition, display and controller
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