IBM powerpc 750gx Manuel D’Utilisation
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_07.fm.(1.2)
March 27, 2006
March 27, 2006
Signal Descriptions
Page 261 of 377
7.2.4.6 Global (GBL)
The global (GBL) signal is an input/output signal on the 750GX.
Global (GBL)—Output
Global (GBL)—Input
State
Asserted
Indicates that the transaction is global and should be snooped by other
masters. GBL reflects the M bit (WIMG bits) from the memory management
unit (MMU) except during certain transactions. Copybacks are always
nonglobal. Instruction accesses do not reflect the M bit when the HID0[IFEM]
bit (HID0 bit 23) is '0' and the instruction address translation bit (bit 26) in the
Machine State Register is '1' (MSR[IR] = '1'); or if HID0[IFEM] is '1' and
MSR[IR] is '0'. In either of these cases, the M bit is ignored and the access is
nonglobal.
masters. GBL reflects the M bit (WIMG bits) from the memory management
unit (MMU) except during certain transactions. Copybacks are always
nonglobal. Instruction accesses do not reflect the M bit when the HID0[IFEM]
bit (HID0 bit 23) is '0' and the instruction address translation bit (bit 26) in the
Machine State Register is '1' (MSR[IR] = '1'); or if HID0[IFEM] is '1' and
MSR[IR] is '0'. In either of these cases, the M bit is ignored and the access is
nonglobal.
Negated
Indicates that the transaction is not global and should not be snooped by
other masters.
other masters.
Timing
Assertion/
Negation/
High
Impedance
Negation/
High
Impedance
The same as A[0–31].
State
Asserted
Indicates that a transaction must be snooped by the 750GX.
Negated
Indicates that a transaction should not be snooped by the 750GX. (In addi-
tion, certain nonglobal transactions are snooped for reservation coherency.
See Table 7-1 on page 256.)
tion, certain nonglobal transactions are snooped for reservation coherency.
See Table 7-1 on page 256.)
Timing
Assertion/
Negation
Negation
The same as A[0–31].