IBM powerpc 750gx Manuel D’Utilisation
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Signal Descriptions
Page 272 of 377
gx_07.fm.(1.2)
March 27, 2006
7.2.10 Reset Signals
There are two reset signals on the 750GX—hard reset (HRESET) and soft reset (SRESET). Descriptions of
the reset signals follows.
the reset signals follows.
7.2.10.1 Hard Reset (HRESET)—Input
The hard reset (HRESET) signal must be used at power-on in conjunction with the test reset (TRST) signal to
properly reset the processor.
properly reset the processor.
7.2.10.2 Soft Reset (SRESET)—Input
The soft reset input provides warm reset capability. This input can be used to avoid forcing the 750GX to
complete the cold start sequence.
complete the cold start sequence.
State
Asserted
Initiates a complete hard reset operation when this input transitions from
asserted to negated. Causes a reset exception as described in
Section 4.5.1, System Reset Exception (0x00100), on page 163 Output
drivers are released to high impedance within five clocks after the assertion
of HRESET.
asserted to negated. Causes a reset exception as described in
Section 4.5.1, System Reset Exception (0x00100), on page 163 Output
drivers are released to high impedance within five clocks after the assertion
of HRESET.
Negated
Indicates that normal operation should proceed.
Timing
Assertion
May occur at any time and may be asserted asynchronously to the 750GX
input clock. Must be held asserted for a minimum of 255 clock cycles after
the PLL lock time has been met. See the 750GX hardware specifications for
further timing comments. Falling-edge activated.
input clock. Must be held asserted for a minimum of 255 clock cycles after
the PLL lock time has been met. See the 750GX hardware specifications for
further timing comments. Falling-edge activated.
Negation
May occur any time after the minimum reset pulse width has been met.
State
Asserted
Initiates processing for a reset exception as described in Section 4.5.1,
System Reset Exception (0x00100), on page 163.
System Reset Exception (0x00100), on page 163.
Negated
Indicates that normal operation should proceed.
Timing
Assertion
May occur at any time and may be asserted asynchronously to the 750GX
input clock. The SRESET input is negative edge-sensitive.
input clock. The SRESET input is negative edge-sensitive.
Negation
May be negated two bus cycles after assertion.