IBM powerpc 750gx Manuel D’Utilisation
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_08.fm.(1.2)
March 27, 2006
March 27, 2006
Bus Interface Operation
Page 303 of 377
8.4.2 Data-Bus Write-Only
As a result of address pipelining, the 750GX can have up to two data tenures queued to perform when it
receives a qualified DBG. Generally, the data tenures should be performed in strict order (the same order as
their address tenures were performed). The 750GX, however, also supports a limited out-of-order capability
with the data-bus write-only (DBWO) input. When recognized on the clock of a qualified DBG, DBWO can
direct the 750GX to perform the next pending data write tenure even if a pending read tenure would have
normally been performed first. For more information on the operation of DBWO, see Section 8.9, Using Data-
Bus Write-Only, on page 320.
receives a qualified DBG. Generally, the data tenures should be performed in strict order (the same order as
their address tenures were performed). The 750GX, however, also supports a limited out-of-order capability
with the data-bus write-only (DBWO) input. When recognized on the clock of a qualified DBG, DBWO can
direct the 750GX to perform the next pending data write tenure even if a pending read tenure would have
normally been performed first. For more information on the operation of DBWO, see Section 8.9, Using Data-
Bus Write-Only, on page 320.
If the 750GX has any data tenures to perform, it always accepts data-bus mastership to perform a data tenure
when it recognizes a qualified DBG. If DBWO is asserted with a qualified DBG and no write tenure is queued
to run, the 750GX still takes mastership of the data bus to perform the next pending read data tenure.
when it recognizes a qualified DBG. If DBWO is asserted with a qualified DBG and no write tenure is queued
to run, the 750GX still takes mastership of the data bus to perform the next pending read data tenure.
Generally, DBWO should only be used to allow a copy-back operation (burst write) to occur before a pending
read operation. If DBWO is used for single-beat write operations, it can negate the effect of the eieio instruc-
tion by allowing a write operation to precede a program-scheduled read operation.
read operation. If DBWO is used for single-beat write operations, it can negate the effect of the eieio instruc-
tion by allowing a write operation to precede a program-scheduled read operation.
8.4.3 Data Transfer
The data-transfer signals include the data bus high (DH[0–31]), data bus low (DL[0–31]), and data bus parity
(DP[0–7]) signals. For memory accesses, the DH and DL signals form a 64-bit data path for read and write
operations.
(DP[0–7]) signals. For memory accesses, the DH and DL signals form a 64-bit data path for read and write
operations.
The 750GX transfers data in either single-beat or 4-beat burst transfers. Single-beat operations can transfer
from 1 to 8 bytes at a time and can be misaligned; see Section 8.3.2.4, Effect of Alignment in Data Transfers,
on page 296. Burst operations always transfer eight words and are aligned on 8-word address boundaries.
Burst transfers can achieve significantly higher bus throughput than single-beat operations.
from 1 to 8 bytes at a time and can be misaligned; see Section 8.3.2.4, Effect of Alignment in Data Transfers,
on page 296. Burst operations always transfer eight words and are aligned on 8-word address boundaries.
Burst transfers can achieve significantly higher bus throughput than single-beat operations.
The type of transaction initiated by the 750GX depends on whether the code or data is cacheable and, for
store operations, whether the cache is in write-back or write-through mode, which software controls on either
a page or block basis. Burst transfers support cacheable operations only. That is, memory structures must be
marked as cacheable (and write-back for data store operations) in the respective page or block descriptor to
take advantage of burst transfers.
store operations, whether the cache is in write-back or write-through mode, which software controls on either
a page or block basis. Burst transfers support cacheable operations only. That is, memory structures must be
marked as cacheable (and write-back for data store operations) in the respective page or block descriptor to
take advantage of burst transfers.
The 750GX output TBST indicates to the system whether the current transaction is a single-beat or 4-beat
transfer (except during eciwx and ecowx transactions, when it signals the state of bit 28 of the External
Access Register (EAR[28]). A burst transfer has an assumed address order. For load or store operations that
miss in the cache (and are marked as cacheable and, for stores, write-back in the MMU), the 750GX uses the
double-word-aligned address associated with the critical code or data that initiated the transaction. This mini-
mizes latency by allowing the critical code or data to be forwarded to the processor before the rest of the
cache line is filled. For all other burst operations, however, the cache line is transferred beginning with the
8-word-aligned data.
transfer (except during eciwx and ecowx transactions, when it signals the state of bit 28 of the External
Access Register (EAR[28]). A burst transfer has an assumed address order. For load or store operations that
miss in the cache (and are marked as cacheable and, for stores, write-back in the MMU), the 750GX uses the
double-word-aligned address associated with the critical code or data that initiated the transaction. This mini-
mizes latency by allowing the critical code or data to be forwarded to the processor before the rest of the
cache line is filled. For all other burst operations, however, the cache line is transferred beginning with the
8-word-aligned data.
8.4.4 Data-Transfer Termination
Four signals are used to terminate data-bus transactions—TA, DRTRY, transfer error acknowledge (TEA),
and ARTRY. The TA signal indicates normal termination of data transactions. It must always be asserted on
the bus cycle coincident with the data that it is qualifying. It can be withheld by the slave for any number of
clocks until valid data is ready to be supplied or accepted. DRTRY indicates invalid read data in the previous
bus clock cycle. DRTRY extends the current data beat and does not terminate it. If it is asserted after the last
and ARTRY. The TA signal indicates normal termination of data transactions. It must always be asserted on
the bus cycle coincident with the data that it is qualifying. It can be withheld by the slave for any number of
clocks until valid data is ready to be supplied or accepted. DRTRY indicates invalid read data in the previous
bus clock cycle. DRTRY extends the current data beat and does not terminate it. If it is asserted after the last