IBM powerpc 750gx Manuel D’Utilisation
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_11.fm.(1.2)
March 27, 2006
March 27, 2006
Performance Monitor and System Related Features
Page 355 of 377
11.2.1.7 Sampled Instruction Address Register (SIA)
The Sampled Instruction Address Register (SIA) is a supervisor-level register that contains the effective
address of an instruction executing at or around the time that the processor signals the performance-monitor
interrupt condition. The SIA is shown in Sampled Instruction Address Register (SIA) on page 75.
address of an instruction executing at or around the time that the processor signals the performance-monitor
interrupt condition. The SIA is shown in Sampled Instruction Address Register (SIA) on page 75.
If the performance-monitor interrupt is triggered by a threshold event, the SIA contains the address of the
exact instruction (called the sampled instruction) that caused the counter to overflow.
exact instruction (called the sampled instruction) that caused the counter to overflow.
If the performance-monitor interrupt was caused by something besides a threshold event, the SIA contains
the address of the last instruction completed during that cycle. SIA can be accessed with the mtspr and
mfspr instructions using SPR 955.
the address of the last instruction completed during that cycle. SIA can be accessed with the mtspr and
mfspr instructions using SPR 955.
11.2.1.8 User Sampled Instruction Address Register (USIA)
The contents of SIA are reflected to USIA, which can be read by user-level software. USIA can be accessed
with the mfspr instructions using SPR 939.
with the mfspr instructions using SPR 939.
11.3 Event Counting
Counting can be enabled if conditions in the processor state match a software-specified condition. Because a
software task scheduler can switch a processor’s execution among multiple processes and because statistics
on only a particular process might be of interest, a facility is provided to mark a process. The performance-
monitor (PM) bit, MSR[29], is used for this purpose. System software can set this bit when a marked process
is running. This enables statistics to be gathered only during the execution of the marked process. The states
of MSR[PR] and MSR[PM] together define a state that the processor (supervisor or program) and the process
(marked or unmarked) can be in at any time. If this state matches a state specified by the MMCR0, the state
for which monitoring is enabled, counting is enabled.
software task scheduler can switch a processor’s execution among multiple processes and because statistics
on only a particular process might be of interest, a facility is provided to mark a process. The performance-
monitor (PM) bit, MSR[29], is used for this purpose. System software can set this bit when a marked process
is running. This enables statistics to be gathered only during the execution of the marked process. The states
of MSR[PR] and MSR[PM] together define a state that the processor (supervisor or program) and the process
(marked or unmarked) can be in at any time. If this state matches a state specified by the MMCR0, the state
for which monitoring is enabled, counting is enabled.
The following states can be monitored:
• Supervisor only
• User only
• Marked and user only
• Not marked and user only
• Marked and supervisor only
• Not marked and supervisor only
• Marked only
• Not marked only
• User only
• Marked and user only
• Not marked and user only
• Marked and supervisor only
• Not marked and supervisor only
• Marked only
• Not marked only
In addition, one of two unconditional counting modes can be specified:
• Counting is unconditionally enabled regardless of the states of MSR[PM] and MSR[PR]. This can be
accomplished by clearing MMCR0[0–4].
• Counting is unconditionally disabled regardless of the states of MSR[PM] and MSR[PR]. This is done by
setting the disable bit (DIS) to 1 (MMCR0[0] = 1).
The performance-monitor counters count specified events and are used to generate performance-monitor
exceptions when an overflow (most-significant bit is a 1) situation occurs. The 750GX performance monitor
has four, 32-bit registers that can count up to 0x7FFFFFFF (2,147,483,648 in decimal) before overflowing.
Bit 0 of the registers is used to determine when an interrupt condition exists.
exceptions when an overflow (most-significant bit is a 1) situation occurs. The 750GX performance monitor
has four, 32-bit registers that can count up to 0x7FFFFFFF (2,147,483,648 in decimal) before overflowing.
Bit 0 of the registers is used to determine when an interrupt condition exists.