Intel architecture ia-32 Manuel D’Utilisation
1-2 Vol. 3A
ABOUT THIS MANUAL
1.2
OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE
A description of this manual’s content follows:
Chapter 1 — About This Manual. Gives an overview of all three volumes of the IA-32 Intel
Architecture Software Developer’s Manual. It also describes the notational conventions in these
manuals and lists related Intel manuals and documentation of interest to programmers and hard-
ware designers.
Architecture Software Developer’s Manual. It also describes the notational conventions in these
manuals and lists related Intel manuals and documentation of interest to programmers and hard-
ware designers.
Chapter 2 — System Architecture Overview. Describes the modes of operation of an IA-32
processor and the mechanisms provided in the IA-32 architecture to support operating systems
and executives, including the system-oriented registers and data structures and the system-
oriented instructions. The steps necessary for switching between real-address and protected
modes are also identified.
processor and the mechanisms provided in the IA-32 architecture to support operating systems
and executives, including the system-oriented registers and data structures and the system-
oriented instructions. The steps necessary for switching between real-address and protected
modes are also identified.
Chapter 3 — Protected-Mode Memory Management. Describes the data structures, registers,
and instructions that support segmentation and paging. The chapter explains how they can be
used to implement a “flat” (unsegmented) memory model or a segmented memory model.
and instructions that support segmentation and paging. The chapter explains how they can be
used to implement a “flat” (unsegmented) memory model or a segmented memory model.
Chapter 4 — Protection. Describes the support for page and segment protection provided in
the IA-32 architecture. This chapter also explains the implementation of privilege rules, stack
switching, pointer validation, user and supervisor modes.
the IA-32 architecture. This chapter also explains the implementation of privilege rules, stack
switching, pointer validation, user and supervisor modes.
Chapter 5 — Interrupt and Exception Handling. Describes the basic interrupt mechanisms
defined in the IA-32 architecture, shows how interrupts and exceptions relate to protection, and
describes how the architecture handles each exception type. Reference information for each
IA-32 exception is given at the end of this chapter.
defined in the IA-32 architecture, shows how interrupts and exceptions relate to protection, and
describes how the architecture handles each exception type. Reference information for each
IA-32 exception is given at the end of this chapter.
Chapter 6 — Task Management. Describes mechanisms the IA-32 architecture provides to
support multitasking and inter-task protection.
support multitasking and inter-task protection.
Chapter 7 — Multiple-Processor Management. Describes the instructions and flags that
support multiple processors with shared memory, memory ordering, and Hyper-Threading Tech-
nology.
support multiple processors with shared memory, memory ordering, and Hyper-Threading Tech-
nology.
Chapter 8 — Advanced Programmable Interrupt Controller (APIC). Describes the
programming interface to the local APIC and gives an overview of the interface between the
local APIC and the I/O APIC.
programming interface to the local APIC and gives an overview of the interface between the
local APIC and the I/O APIC.
Chapter 9 — Processor Management and Initialization. Defines the state of an IA-32
processor after reset initialization. This chapter also explains how to set up an IA-32 processor
for real-address mode operation and protected- mode operation, and how to switch between
modes.
processor after reset initialization. This chapter also explains how to set up an IA-32 processor
for real-address mode operation and protected- mode operation, and how to switch between
modes.
Chapter 10 — Memory Cache Control. Describes the general concept of caching and the
caching mechanisms supported by the IA-32 architecture. This chapter also describes the
memory type range registers (MTRRs) and how they can be used to map memory types of phys-
ical memory. Information on using the new cache control and memory streaming instructions
introduced with the Pentium III, Pentium 4, and Intel Xeon processors is also given.
caching mechanisms supported by the IA-32 architecture. This chapter also describes the
memory type range registers (MTRRs) and how they can be used to map memory types of phys-
ical memory. Information on using the new cache control and memory streaming instructions
introduced with the Pentium III, Pentium 4, and Intel Xeon processors is also given.
Chapter 11 — Intel
®
MMX™ Technology System Programming. Describes those aspects of
the Intel
®
MMX™ technology that must be handled and considered at the system programming