Intel X5675 BX80614X5675 Manuel D’Utilisation
Codes de produits
BX80614X5675
Electrical Specifications
30
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
• that share symmetry across physical packages with respect to the number of
logical processor per package, number of cores per package, number of Intel
®
QuickPath interfaces, and cache topology.
• that have identical Extended Family, Extended Model, Processor Type, Family Code
and Model Number as indicated by the Function 1 of the CPUID instruction.
Note:
Processors must operate with the same Intel
®
QuickPath Interconnect, DDR3 memory
and core frequency.
While Intel does nothing to prevent processors from operating together, some
combinations may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel
combinations may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel
®
Xeon
®
5600
series processor attributes, the following population rules and stepping matrix have
been developed to clearly define supported configurations.
been developed to clearly define supported configurations.
• Processors must be of the same power-optimization segment. This insures
processors include the same maximum Intel
®
QuickPath Interconnect and DDR3
operating speeds and cache sizes.
• Processors must operate at the same core frequency. Note, processors within the
same power-optimization segment supporting different maximum core frequencies
can be operated within a system. However, both must operate at the highest
frequency rating commonly supported. Mixing components operating at different
internal clock frequencies is not supported and will not be validated by Intel.
can be operated within a system. However, both must operate at the highest
frequency rating commonly supported. Mixing components operating at different
internal clock frequencies is not supported and will not be validated by Intel.
• Processors must share symmetry across physical packages with respect to the
number of logical processors per package, number of cores per package (but not
necessarily the same subset of cores within the packages), number of Intel
necessarily the same subset of cores within the packages), number of Intel
®
QuickPath interfaces and cache topology.
• Mixing steppings is only supported with processors that have identical Extended
Family, Extended Model, Processor Type, Family Code and Model Number as
indicated by the Function 1 of the CPUID instruction. Mixing processors of different
steppings, but the same mode (as per CPUID instruction) is supported. Details
regarding the CPUID instruction are provide in the Intel
indicated by the Function 1 of the CPUID instruction. Mixing processors of different
steppings, but the same mode (as per CPUID instruction) is supported. Details
regarding the CPUID instruction are provide in the Intel
®
64 and IA-32
Architectures Software Developer’s Manual, Volume 2A.
• After AND’ing the feature flag and extended feature flags from the installed
processors, any processor whose set of feature flags exactly matches the AND’ed
feature flags can be selected by the BIOS as the BSP. If no processor exactly
matches the AND’ed feature flag values, then the processor with the numerically
lower CPUID should be selected as the BSP.
feature flags can be selected by the BIOS as the BSP. If no processor exactly
matches the AND’ed feature flag values, then the processor with the numerically
lower CPUID should be selected as the BSP.
• Intel requires that the proper microcode update be loaded on each processor
operating within the system. Any processor that does not have the proper
microcode update loaded is considered by Intel to be operating out-of-specification.
microcode update loaded is considered by Intel to be operating out-of-specification.
• Customers are fully responsible for the validation of their system configurations
Note:
Processors within a system must operate at the same frequency per bits [15:8] of the
FLEX_RATIO MSR (Address: 194h); however this does not apply to frequency
transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep
2.4
Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
processor will have over certain time periods. The values are only estimates and actual
specifications for future processors may differ. Processors may or may not have
processor will have over certain time periods. The values are only estimates and actual
specifications for future processors may differ. Processors may or may not have