Intel E7-4860 AT80615007254AA Manuel D’Utilisation

Codes de produits

AT80615007254AA

Datasheet Volume 2 of 2

9.1.1

Thermal Monitoring - 2 (TM2)...................................................................39

9.1.2

Thermal Monitoring - 1 (TM1) and T-state ..................................................39

9.1.3

THERMTRIP# .........................................................................................40

9.1.4

PROCHOT# ............................................................................................40

9.1.5

FORCEPR#.............................................................................................40

9.1.6

PECI .....................................................................................................40

9.2

Idle State Power Management .............................................................................40
9.2.1

Overview ...............................................................................................40

9.2.2

C-State Support .....................................................................................41

9.3

Core C6 Support................................................................................................45
9.3.1

Core C6.................................................................................................45

9.3.2

Core C6 Entry/Exit Flow...........................................................................45

9.4

Package C6 Support ...........................................................................................45
9.4.1

Introduction...........................................................................................46

9.5

Package C3/Package C6 with Memory Self Refresh .................................................46
9.5.1

Package C3/C6 Memory Self-Refresh Limitations.........................................46

9.5.2

PMReq Retry/CmpD Response Behavior .....................................................47

9.6

S-State Support ................................................................................................48
9.6.1

Overview ...............................................................................................48

9.7

APIC Timer .......................................................................................................48

9.8

PECI Sideband P-state Control.............................................................................48
9.8.1

Overview ...............................................................................................48

9.8.2

MAILBOX_WRITE_P_STATE_LIMIT (request type = 0x23) ............................48

9.8.3

MAILBOX_READ_P_STATE_LIMIT (request type = 0x24) ..............................49

Figures

2-1

Intel

Xeon

Processor 7500 Series-Based Platform Block Diagram,

Four-socket Two-IOH Configuration......................................................................14

2-2

Intel® Xeon® Processor E7-8800/4800/2800 Product Families Block Diagram ...........16

4-1

Intel Xeon Processor E7-8800/4800/2800 Product Families Block Diagram ................21

5-1

Intel Xeon Processor E7-8800/4800/2800 Product Families Block Diagram ................25

6-1

Intel Xeon Processor E7-8800/4800/2800 Product Families Block Diagram ................29

7-1

Partial Memory Mirroring (Within a Socket) ...........................................................34

7-2

Partial Memory Mirroring (Between Connected Sockets) ..........................................34

8-1

Intel Xeon Processor E7-8800/4800/2800 Product Families System Interface.............38

9-1

Valid Thread/Core Architectural C-State Transitions................................................42

Tables

1-1

Abbreviation Summary ........................................................................................ 9

2-1

Intel

Xeon

Processor E7-8800/4800/2800 Product Families and

Intel

Xeon

Processor 7500 Series Key Features .................................................13

2-2

System Interface Functional Blocks ......................................................................16

3-1

Target List Index ...............................................................................................17

3-2

NodeID Formation .............................................................................................17

3-3

I/O Decoder Entries ...........................................................................................18

4-1

RTID Generation 10 LLC (Last Level Cache) Slices..................................................22

4-2

RTID Generation 8 LLC (Last Level Cache) Slices....................................................22

4-3

RTID Generation 6 LLC (Last Level Cache) Slices....................................................23

5-1

Tracker Allocation Modes ....................................................................................26

5-2

TID Assignment Restrictions................................................................................26

9-1

Core C-State Resolution......................................................................................42

9-2

Package C-State Resolution.................................................................................43