Sierra Wireless Q2687 Manuel D’Utilisation
Wireless CPU Quik Q2687
Interfaces
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WA_ENG_Q2687_PTS_001-002
September 11, 2006
Pin description
Signal
Pin
number
I/O
I/O type
Reset
state
Description
Multiplexed
with
SCL 44
O
Open
drain
Z
Serial
Clock
GPIO26
SDA 46
I/O
Open
drain
Z
Serial
Data GPIO27
See section 3.3, "Electrical information for digital I/O" for Open drain, 2V8 and 1V8 voltage characteristics
and Reset state definition.
3.5 Parallel Interface
The Wireless CPU Quik Q2687 offers a 16-bit wide parallel bus interface.
Few signals are multiplexed. It is possible to have these configurations.
For software information, see the document [4].
• CS3*, A1, GPIO1, GPIO2
• CS3*, A1, A24, GPIO1
• CS3*, A1, A24, A25
• CS3*, CS2*, A1, GPIO2
• CS3*, CS2*, A1, A24
• CS3*, A1, A24, GPIO1
• CS3*, A1, A24, A25
• CS3*, CS2*, A1, GPIO2
• CS3*, CS2*, A1, A24