HARRIS CORPORATION TR-391-A2 Manuel D’Utilisation
3-1 Reference Oscillator
The reference oscillator consists of a 1.5-PPM TCXO (Temperature Controlled Compensated Crystal
Oscillator). The standard reference oscillator frequency is 12.8MHz.
The TCXO is enclosed in a RF shielded can. The TCXO is compensated by internal temperature compensated
circuit for both low and high temperature. With no additional compensated the oscillator will provide 1.5 PPM
stability from -30
The reference oscillator consists of a 1.5-PPM TCXO (Temperature Controlled Compensated Crystal
Oscillator). The standard reference oscillator frequency is 12.8MHz.
The TCXO is enclosed in a RF shielded can. The TCXO is compensated by internal temperature compensated
circuit for both low and high temperature. With no additional compensated the oscillator will provide 1.5 PPM
stability from -30
°
C to +60
°
C.
3-2 PLL Frequency Synthesizer chip
PLL Frequency Synthesizer chip IC305 contains a programmable reference oscillator divider (R), phase
detector, and programmable VCO dividers (+N, A).
A fixed integer number to obtain a 6.25KHz or 5KHz channel reference for the synthesizer divides the
reference frequency 12.8MHz from the reference oscillator.
PC PROGRAMMER can change this divide value.
The internal phase detector compares the output of the reference divider with the output of internal +N,A
counter. The +N, A count counter receives as its input the VCO frequency divided by the Prescaler and
programmed by the microcomputer.
This results in an error voltage when the phase differ and a constant output voltage when phase-detector input
compare in frequency and phase.
If a phase error is detected, an error voltage is developed and applied to the VCO DC offset and loop filter to
reset the VCO frequency. The count of the +N, A counters is controlled by the frequency data received on the
SCK-, SDT- and PLLENB- line from SYSTEM CONTROL UNIT.
When a different channel is selected or when changing to the transmit or receive mode an error voltage is
generated and appears at the phase-detector output, APD(IC305-2pin), causing the Phase Locked Loop to
acquire the new frequency.
PLL Frequency Synthesizer chip IC305 contains a programmable reference oscillator divider (R), phase
detector, and programmable VCO dividers (+N, A).
A fixed integer number to obtain a 6.25KHz or 5KHz channel reference for the synthesizer divides the
reference frequency 12.8MHz from the reference oscillator.
PC PROGRAMMER can change this divide value.
The internal phase detector compares the output of the reference divider with the output of internal +N,A
counter. The +N, A count counter receives as its input the VCO frequency divided by the Prescaler and
programmed by the microcomputer.
This results in an error voltage when the phase differ and a constant output voltage when phase-detector input
compare in frequency and phase.
If a phase error is detected, an error voltage is developed and applied to the VCO DC offset and loop filter to
reset the VCO frequency. The count of the +N, A counters is controlled by the frequency data received on the
SCK-, SDT- and PLLENB- line from SYSTEM CONTROL UNIT.
When a different channel is selected or when changing to the transmit or receive mode an error voltage is
generated and appears at the phase-detector output, APD(IC305-2pin), causing the Phase Locked Loop to
acquire the new frequency.
3-3 Loop filter
The Loop filter consists of R352 through R349 and C379, C380 and C378.
This filter controls the bandwidth and stability of the synthesizer loop.
When a different channel changing or changing to the transmit or receive mode, FET switch is controlled by
PLLFST- for PLL lock up first (aplox 9mSEC).
The output of the filter is applied to the varicaps in the transmit and receive VCO’s to adjust and maintain the
VCO frequency. The use of to VCO’s allows rapid independent selection of transmit and receive frequencies
across the frequency split.
The Loop filter consists of R352 through R349 and C379, C380 and C378.
This filter controls the bandwidth and stability of the synthesizer loop.
When a different channel changing or changing to the transmit or receive mode, FET switch is controlled by
PLLFST- for PLL lock up first (aplox 9mSEC).
The output of the filter is applied to the varicaps in the transmit and receive VCO’s to adjust and maintain the
VCO frequency. The use of to VCO’s allows rapid independent selection of transmit and receive frequencies
across the frequency split.