Intel III Xeon 500 MHz 80525KX500512 Manuel D’Utilisation

Codes de produits

80525KX500512

Datasheet

Pentium

III Xeon™ Processor at 500 and 550 MHz

Top View of Cartridge Insertion Pressure Points ................................................61

Front View of Connector Mating Details..............................................................61

Boxed Pentium

III Xeon™ Processor................................................................71

Side View Space Requirements for the Boxed Processor ..................................72

Front View Space Requirements for the Boxed Processor .................................73

Front Views of the Boxed Processor with Attached Auxiliary Fan
(Not Included with Boxed Processor) ..................................................................75

Front View of Boxed Processor Heatsink with Fan Attach Features
(Fan Not Included)...............................................................................................75

Cross-sectional View of Grommet Attach Features in the Heatsink
(Grommet Shown) ...............................................................................................76

Side View Space Recommendation for the Auxiliary Fan ...................................76

Front View Space Recommendations for the Auxiliary Fan ................................77

Boxed Processor Fan/Heatsink Power Cable Connector Description.................77

Hardware Components of an ITP........................................................................79

AGTL+ Signal Termination ..................................................................................82

TCK with Individual Buffering Scheme ................................................................84

System Preferred Debug Port Layout .................................................................85

PWRGOOD Relationship at Power-On ...............................................................94

Tables

Core Frequency to System Bus Multiplier Configuration.....................................14

Core and L2 Voltage Identification Definition ......................................................16

Pentium

III Xeon™ Processor System Bus Pin Groups....................................18

Pentium

III Xeon™ Processor Absolute Maximum Ratings ..............................20

Voltage Specifications ........................................................................................21

Current Specifications .........................................................................................22

AGTL+ Signal Groups, DC Specifications at the Processor Core.......................23

CMOS, TAP, Clock and APIC Signal Groups, DC Specifications at the
Processor Core ...................................................................................................24

SMBus Signal Group, DC Specifications at the Processor Core ........................24

Pentium

III Xeon™ Processor Internal Parameters for the AGTL+ Bus............25

System Bus AC Specifications (Clock) at the Processor Core............................25

AGTL+ Signal Groups, System Bus AC Specifications at the Processor Core... 26

CMOS, TAP, Clock and APIC Signal Groups, AC Specifications at the
Processor Core ...................................................................................................26

System Bus AC Specifications (Reset Conditions) .............................................27

System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor
Core.....................................................................................................................27

System Bus AC Specifications (TAP Connection) at the Processor Core ..........28

SMBus Signal Group, AC Specifications at the Edge Fingers ............................28

BCLK Signal Quality Specifications for Simulation at the Processor Core..........33

AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor
Core.....................................................................................................................34

AGTL+ Overshoot/Undershoot Guidelines at the Processor Core......................35

2.5 V Tolerant Signal Overshoot/Undershoot Guidelines at the Processor Core35

Signal Ringback Specifications for 2.5V Tolerant Signal Simulation at the
Processor Core ...................................................................................................36

Processor Information ROM Format ...................................................................41

Current Address Read SMBus Packet ................................................................43

Random Address Read SMBus Packet ..............................................................43