Silicon Power 2GB PC2-6400 SP002GBLRU800S02 Manuel D’Utilisation
Codes de produits
SP002GBLRU800S02
SP002GBLRU800S02
240pin DDR2 800 Unbuffered DIMM
This document is a general product description and is subject to change without notice
4
6. Pin Description
SYMBOL
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and
/CK
are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of
/CK
. Output data (DQs and DQS
/DQS) is referenced to the crossings of CK and
/CK
.
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh.
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh.
/S0 Input
Chip Select: Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
ODT Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, and /DQS. The ODT
input will be ignored if disabled via the LOAD MODE command.
SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, and /DQS. The ODT
input will be ignored if disabled via the LOAD MODE command.
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered.
DM0-DM7
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
BA0 - BA2
Input
Bank Address Inputs: BA0 and BA1 for 256 and 512Mb, BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also determines if the
mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
Active, Read, Write or Precharge command is being applied. Bank address also determines if the
mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
A0 - A15
Input
Address Inputs: Provided the row address for Active commands and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the
Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be
precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code
during Mode Register Set commands.
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the
Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be
precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code
during Mode Register Set commands.
DQ0-DQ63
Input/Output
Data bit Input/ Output: Bi-directional data bus.
DQS0-DQS7
/DQS0-/DQS7 Input/Output
Data Strobe: output with read data, input with write data for source-synchronous operation.
Edge-aligned with read data, center-aligned with write data. For Rawcards using x16 orginized
DRAMs DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the
DRAM
DRAMs DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the
DRAM
NC
No Connect: No internal electrical connection is present.
V
DDQ
Supply
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all
current DDR2 unbuffered DIMM designs,
current DDR2 unbuffered DIMM designs,
V
DDQ
shares the same power plane as
V
DD
pins
V
DD
,
V
SS
Supply
Power and ground for the DDR2 SDRAM input buffers, and core logic.
V
DD
and
V
DDQ
pins are tied to
V
DD
/
V
DDQ
planes on these modules.
V
REF
Supply
Reference voltage for SSTL 18 inputs.
SDA
Input/Output
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to
connected from the SDA bus line to
V
DD
to act as a pullup on the system board.
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to
from the SCL bus time to
V
DD
to act as a pullup onthe system board.
V
DD
SPD
Supply
Power supply for SPD EEPROM. This supply is separate from the
V
DD
/
V
DDQ
power plane.
EEPROM supply is operable from 1.7V to 3.6V.
SA0-SA2
Input
These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EERPOM
address range
address range