HP A2Y15AV Manuel D’Utilisation

118

Datasheet, Volume 2

The register indicates PCI Express* link status.

15

RW1C

0b

Uncore

Link Autonomous Bandwidth Status (LABWS) 
This bit is set to 1b by hardware to indicate that hardware has 

autonomously changed link speed or width, without the port 

transitioning through DL_Down status, for reasons other than to 

attempt to correct unreliable link operation. 
This bit must be set if the Physical Layer reports a speed or width 

change was initiated by the downstream component that was 

indicated as an autonomous change. 

14

RW1C

0b

Uncore

Link Bandwidth Management Status (LBWMS) 
This bit is set to 1b by hardware to indicate that either of the 

following has occurred without the port transitioning through 

DL_Down status:

• A link retraining initiated by a write of 1b to the Retrain Link 

bit has completed. 

Note: This bit is set following any write of 1b to the Retrain 

Link bit, including when the Link is in the process of 

retraining for some other reason. 

• Hardware has autonomously changed link speed or width to 

attempt to correct unreliable link operation, either through 

an LTSSM time-out or a higher level process.

This bit must be set if the Physical Layer reports a speed or width 

change was initiated by the downstream component that was not 

indicated as an autonomous change. 

13

RO-V

0b

Uncore

Data Link Layer Link Active (Optional) (DLLLA) 
This bit indicates the status of the Data Link Control and 

Management State Machine. It returns a 1b to indicate the 

DL_Active state, 0b otherwise. 
This bit must be implemented if the corresponding Data Link 

Layer Active Capability bit is implemented. Otherwise, this bit 

must be hardwired to 0b.

12

RO

1b

Uncore

Slot Clock Configuration (SCC) 
0 = The device uses an independent clock irrespective of the 

presence of a reference on the connector.

1 = The device uses the same physical reference clock that the 

platform provides on the connector.

11

RO-V

0b

Uncore

Link Training (LTRN) 
When set, this bit indicates that the Physical Layer LTSSM is in 

the Configuration or Recovery state, or that 1b was written to the 

Retrain Link bit but Link training has not yet begun. Hardware 

clears this bit when the LTSSM exits the Configuration/Recovery 

state once Link training is complete.