HP A2Y15AV Manuel D’Utilisation

Datasheet, Volume 2

127

Processor Configuration Registers 

31:12

RO

0h

11

RO

1b

Uncore

Supported (LTRS) 
A value of 1b indicates support for the optional Latency Tolerance 

& Bandwidth Requirement Reporting (LTBWR) mechanism 

capability. 
Root Ports, Switches and Endpoints are permitted to implement 

this capability. For Switches that implement LTBWR, this bit must 

be set only at the upstream port.
For a multi-Function device, each Function must report the same 

value for this bit.
For Bridges, Downstream Ports, and components that do not 

implement this capability, this bit must be hardwired to 0b.

10:6

RO

0h

5

RW-O

0b

Uncore

ARI Forwarding Supported (ARIFS)
Applicable only to Switch Downstream Ports and Root Ports; must 

be 0b for other Function types. This bit must be set to 1b if a 

Switch Downstream Port or Root Port supports this optional 

capability. 

4

RO

0b

Uncore

Completion Time-out Disabled Supported (CTODS)
A value of 1b indicates support for the Completion Timeout 

Disable mechanism.
The Completion Timeout Disable mechanism is required for 

Endpoints that issue Requests on their own behalf and PCI 

Express to PCI/PCI-X Bridges that take ownership of Requests 

issued on PCI Express.
This mechanism is optional for Root Ports.
The Root port does not support completion timeout disable.

3:0

RO

0000b

Uncore

Completion Timer Ranges Supported (CTOR) 
Device Function support for the optional Completion Timeout 

programmability mechanism. This mechanism allows system 

software to modify the Completion Timeout value.
This field is applicable only to Root Ports, Endpoints that issue 

Requests on their own behalf, and PCI Express to PCI/PCI-X 

Bridges that take ownership of Requests issued on PCI Express. 

For all other Functions this field is reserved and must be 

hardwired to 0000b.
0000b = Completion Timeout programming not supported – the 

Function must implement a time-out value in the range 50 μs to 

50 ms.