HP A2Y15AV Manuel D’Utilisation
Datasheet, Volume 2
157
Processor Configuration Registers
2.8.14
SID2—Subsystem Identification Register
This register is used to uniquely identify the subsystem where the PCI device resides.
2.8.15
ROMADR—Video BIOS ROM Base Address Register
The IGD does not use a separate BIOS ROM; therefore this register is hardwired to 0s.
2.8.16
CAPPOINT—Capabilities Pointer Register
This register points to a linked list of capabilities implemented by this device.
B/D/F/Type:
0/2/0/PCI
Address Offset:
2E–2Fh
Reset Value:
0000h
Access:
RW-O
Size:
16 bits
Bit
Access
Reset
Value
RST/
PWR
Description
15:0
RW-O
0000h
Uncore
Subsystem Identification (SUBID)
This value is used to identify a particular subsystem. This field
This value is used to identify a particular subsystem. This field
should be programmed by BIOS during boot-up. Once written,
this register becomes Read-only. This register can only be cleared
by a Reset.
B/D/F/Type:
0/2/0/PCI
Address Offset:
30–33h
Reset Value:
00000000h
Access:
RO
Size:
32 bits
BIOS Optimal Default
000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:18
RO
0000h
Uncore
ROM Base Address (RBA)
Hardwired to 0s.
Hardwired to 0s.
17:11
RO
00h
Uncore
Address Mask (ADMSK)
Hardwired to 0s to indicate 256 KB address range.
Hardwired to 0s to indicate 256 KB address range.
10:1
RO
0h
Reserved (RSVD)
0
RO
0b
Uncore
ROM BIOS Enable (RBE)
0 = ROM not accessible.
0 = ROM not accessible.
B/D/F/Type:
0/2/0/PCI
Address Offset:
34h
Reset Value:
90h
Access:
RO-V
Size:
8 bits
Bit
Access
Reset
Value
RST/
PWR
Description
7:0
RO-V
90h
Uncore
Capabilities Pointer Value (CPV)
This field contains an offset into the function's PCI Configuration
This field contains an offset into the function's PCI Configuration
Space for the first item in the New Capabilities Linked List, the
MSI Capabilities ID registers at address 90h or the Power
Management capability at D0h.
This value is determined by the configuration in CAPL[0].
This value is determined by the configuration in CAPL[0].