HP A2Y15AV Manuel D’Utilisation
Processor Configuration Registers
24
Datasheet, Volume 2
2.3.2.4
DRAM Protected Range (DPR)
This protection range only applies to DMA accesses and GMADR translations. It serves a
purpose of providing a memory range that is only accessible to processor streams.
purpose of providing a memory range that is only accessible to processor streams.
The DPR range works independent of any other range, including the PMRC checks in
VTd. It occurs post any VTd translation. Therefore, incoming cycles are checked against
this range after the VTd translation and faulted if they hit this protected range, even if
they passed the VTd translation.
VTd. It occurs post any VTd translation. Therefore, incoming cycles are checked against
this range after the VTd translation and faulted if they hit this protected range, even if
they passed the VTd translation.
The system will set up:
• 0 to (TSEG_BASE – DPR size – 1) for DMA traffic
• TSEG_BASE to (TSEG_BASE – DPR size) as no DMA.
• TSEG_BASE to (TSEG_BASE – DPR size) as no DMA.
After some time, software could request more space for not allowing DMA. It will get
some more pages and make sure there are no DMA cycles to the new region. DPR size
is changed to the new value. When it does this, there should not be any DMA cycles
going to DRAM to the new region.
some more pages and make sure there are no DMA cycles to the new region. DPR size
is changed to the new value. When it does this, there should not be any DMA cycles
going to DRAM to the new region.
If there were cycles from a rogue device to the new region, then those could use the
previous decode until the new decode can ensure PV. No flushing of cycles is required.
On a clock by clock basis proper decode with the previous or new decode needs to be
ensured.
previous decode until the new decode can ensure PV. No flushing of cycles is required.
On a clock by clock basis proper decode with the previous or new decode needs to be
ensured.
All upstream cycles from 0 to (TSEG_BASE – 1 – DPR size), and not in the legacy holes
(VGA), are decoded to DRAM.
(VGA), are decoded to DRAM.
Because Bus Master cycles can occur when the DPR size is changed, the DPR size needs
to be treated dynamically.
to be treated dynamically.
2.3.2.5
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode,
legacy VGA graphics compatibility, and graphics GTT stolen memory. It is the
responsibility of BIOS to properly initialize these regions.
reside within system memory address range (< TOLUD) are created for SMM-mode,
legacy VGA graphics compatibility, and graphics GTT stolen memory. It is the
responsibility of BIOS to properly initialize these regions.
2.3.2.6
Graphics Stolen Spaces
2.3.2.6.1
GTT Stolen Space (GSM)
GSM is allocated to store the graphics (GFX) translation table entries.
GSM always exists regardless of VT-d as long as internal graphics is enabled. This space
is allocated to store accesses as page table entries are getting updated through virtual
GTTMMADR range. Hardware is responsible to map PTEs into this physical space.
is allocated to store accesses as page table entries are getting updated through virtual
GTTMMADR range. Hardware is responsible to map PTEs into this physical space.
Direct accesses to GSM are not allowed; only hardware translations and fetches can be
directed to GSM.
directed to GSM.