HP A2Y15AV Manuel D’Utilisation
Datasheet, Volume 2
249
Processor Configuration Registers
2.14.5
TC_RFP_C1—Refresh Parameters Register
This register provides refresh parameters.
B/D/F/Type:
0/0/0/MCHBAR MC1
Address Offset:
4694–4697h
Reset Value:
0000980Fh
Access:
RW-L
Size:
32 bits
BIOS Optimal Default
0000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:18
RO
0h
Reserved (RSVD)
17:16
RW-L
00b
Uncore
Double Refresh Control (DOUBLE_REFRESH_CONTROL)
This field will allow the double self refresh enable/disable.
00 = Double refresh rate when DRAM is WARM/HOT.
01 = Force double self refresh regardless of temperature.
10 = Disable double self refresh regardless of temperature.
11 = Reserved
This field will allow the double self refresh enable/disable.
00 = Double refresh rate when DRAM is WARM/HOT.
01 = Force double self refresh regardless of temperature.
10 = Disable double self refresh regardless of temperature.
11 = Reserved
15:12
RW-L
9h
Uncore
Refresh panic WM (Refresh_panic_wm)
tREFI count level in which the refresh priority is panic (default is
tREFI count level in which the refresh priority is panic (default is
9)
It is recommended to set the panic WM at least to 9, in order to
It is recommended to set the panic WM at least to 9, in order to
use the maximum no-refresh period possible
11:8
RW-L
8h
Uncore
Refresh high priority WM (Refresh_HP_WM)
tREFI count level that turns the refresh priority to high (default is
tREFI count level that turns the refresh priority to high (default is
8)
7:0
RW-L
0Fh
Uncore
Rank idle timer for opportunistic refresh (OREF_RI)
Rank idle period that defines an opportunity for refresh, in DCLK
Rank idle period that defines an opportunity for refresh, in DCLK
cycles