Intel i3-3130M AW8063801111500 Manuel D’Utilisation

Datasheet, Volume 1

53

C1/C1E is a low power state entered when all threads within a core execute a HLT or 
MWAIT(C1/C1E) instruction.

A System Management Interrupt (SMI) handler returns execution to either Normal 
state or the C1/C1E state. See the Intel

Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.

While a core is in C1/C1E state, it processes bus snoops and snoops from other 
threads. For more information on C1E, see 

.

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to 
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its 
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while 
maintaining its architectural state. All core clocks are stopped at this point. Because the 
core’s caches are flushed, the processor does not wake any core that is in the C3 state 
when either a snoop is detected or when another core accesses cacheable memory.

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an 
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural 
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero 
volts. During exit, the core is powered on and its architectural state is restored.

In general, deeper C-states such as C6 have long latencies and have higher energy 
entry / exit costs. The resulting performance and energy penalties become significant 
when the entry / exit frequency of a deeper C-state is high. Therefore, incorrect or 
inefficient usage of deeper C-states have a negative impact on idle power. To increase 
residency and improve idle power in deeper C-states, the processor supports C-state 
auto-demotion.

There are two C-State auto-demotion options:

• C6 to C3
• C6/C3 To C1

The decision to demote a core from C6 to C3 or C3/C6to C1 is based on each core’s 
immediate residency history. Upon each core C6 request, the core C-state is demoted 
to C3 or C1 until a sufficient amount of residency has been established. At that point, a 
core is allowed to go into C3/C6. Each option can be run concurrently or individually.

This feature is disabled by default. BIOS must enable it in the 
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by 
this register.