Super Talent Technology 2GB DDR3-1333 W1333UA2GV Manuel D’Utilisation
Codes de produits
W1333UA2GV
240-Pin Unbuffered DIMM DDR3 SDRAM
http://www.supertalent.com/oem
Products and Specifications discussed herein are subject to change without notice
9.0 AC & DC Operating Conditions
Recommended operating conditions (Voltage referenced to Vss=0V, TA=0 to 70°C)
Symbol
Parameter
Min
Typ
Max
Unit
V
DD
Supply Voltage
1.425
1.5
1.575
V
V
DDQ
Supply Voltage for Output
1.425
1.5
1.575
V
V
REF
DQ
(DC)
I/O Reference Voltage (DQ)
0.49*V
DDQ
0.50*V
DDQ
0.51*V
DDQ
V
V
REF
CA
(DC)
I/O Reference Voltage (CMD/Add)
0.49*V
DDQ
0.50*V
DDQ
0.51*V
DDQ
V
V
TT
Termination Voltage
0.49*V
DDQ
0.50*V
DDQ
0.51*V
DDQ
V
10.0 Capacitance (Max.)
Symbol
Parameter/Condition
Min
Max
Unit
CCK
Input capacitance, CK and CK
-
11
pF
CI1
Input capacitance, CKE and CS
-
12
pF
CI2
Input capacitance, Addr, RAS, CAS, WE
-
12
pF
CIO
Input capacitance, DQ, DM, DQS, DQS
-
10
pF
11.1 AC Timing Parameters & Specifications
(AC operating conditions unless otherwise noted)
DDR3-1333
Parameter
Symbol
min
max
Units
Minimum Clock Cycle Time (DLL off mode)
tCK(DLL_OFF)
8 -
ns
Average Clock Period
tCK(avg)
-
ps
Clock Period
tCK(abs)
t
CK
(avg) min +t
JIT
(per)min
tCK(avg) max +tJIT
(per)max
ps
Average high pulse width
tCH(avg)
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
tCK(avg)
Clock Period Jitter
tJIT(per)
-80 80
ps
Clock Period Jitter during DLL locking period
tJIT(per, lck)
-80 80
ps
Cycle to Cycle Period Jitter
tJIT(cc)
160 -
ps
Cycle to Cycle Period Jitter during DLL locking period
tJIT(cc, lck)
140 -
ps
Cumulative error across 2 cycles
tERR(2per)
- 118
118
ps
Cumulative error across 3 cycles
tERR(3per)
- 140
140
ps
Cumulative error across 4 cycles
tERR(4per)
- 155
155
ps
Cumulative error across 5 cycles
tERR(5per)
- 168
168
ps
Cumulative error across 6 cycles
tERR(6per)
- 177
177
ps
Cumulative error across 7 cycles
tERR(7per)
- 186
186
ps
Cumulative error across 8 cycles
tERR(8per)
- 193
193
ps
Cumulative error across 9 cycles
tERR(9per)
- 200
200
ps
Cumulative error across 10 cycles
tERR(10per)
- 205
205
ps
6
© 2006 Super Talent Tech., Corporation.