Intel G1620T CM8063701448300 Manuel D’Utilisation

Datasheet

701

— Express Card Hot Plug Events

— System Error Events

•

Power Management

— Link State support for L0s, L1 and L2

— Powered down in ACPI S3 state - L3

Depending on SKU, there are up to four possible lane assignments for root ports 1-4.

Root port configurations are set by SoftStraps stored in SPI flash, and the default 
option is “(4) x1”. Links for each root port will train automatically to the maximum 
possible for each port.

x2 link widths are not common. Most devices will only train to x1 or x4.

PCI functions in PCI configuration space are disabled for root ports not available.

A root port is capable of handling interrupts and events from an end point device. A 
root port can also generate its own interrupts for some events, including power 
management and hot plug events, but also including error events.

There are two interrupt types a root port will receive from an end point device: INTx 
(legacy), and MSI. MSI’s are automatically passed upstream by the root port, just as 
other memory writes would be. INTx messages are delivered to the Legacy block’s 
interrupt router/controller by the root port.

PCIe* 2.0

RP 1

RP 2

RP 3

RP 4

Lane 0 Lane 1 Lane 2 Lane 3

PCIe* 2.0

Root Port 1

Root Port 2

Lane 0 Lane 1 Lane 2 Lane 3

PCIe* 2.0

Root Port 1

RP 2

RP 3

Lane 0 Lane 1 Lane 2 Lane 3

PCIe* 2.0

Root Port 1

Lane 0 Lane 1 Lane 2 Lane 3

(4) x1

(1) x2, (2) x1

(2) x2

(1) x4