Intel G1620T CM8063701448300 Manuel D’Utilisation

Datasheet

81

 list the DC specifications for the processor power rails. They are 

valid only while meeting specifications for junction temperature, clock frequency, and 
input voltages. Care should be taken to read all notes associated with each parameter.

1.

Unless otherwise noted, all specifications in this table are based on estimates and simulations or 

empirical data. These specifications will be updated with characterized data from silicon measurements 

at a later date.

2.

Each processor is programmed with voltage identification value (VID), which is set at manufacturing 

and cannot be altered. Individual VID values are calibrated during manufacturing such that two SoCs at 

the same frequency may have different settings within the VID range. This differs from the VID 

employed by the processor during a power management event.

3.

These are pre-silicon estimates and are subject to change.

4.

See the VR12/IMVP7 Pulse Width Modulation specification for additional details. Either value is ok.

5.

N/A

J2900 - Quad Core Pentium

13.5 A

11 A

J1900 - Quad Core Celeron

10.5 A

11 A

J1800 - Dual Core Celeron

7 A

10.5 A

CORE_VCC VID

Core VID Target Range

0.40

1.14

V

CORE_VCC_S3

V

CC

 for Processor Core

See VCC VID

V

2, 3, 5

UNCORE_VNN VID

Uncore VID Target Range

0.50

1.05

V

UNCORE_VNN_S3

V

NN

 for Processor Uncore

See VNN VID

V

2, 3, 5

CORE_VCC/

UNCORE_VNN
V

BOOT

Default target V

CC

/V

NN 

voltage for 

initial power up.

1.0 or

1.1

V

4

SLOPE

LL

Processor Core Supply DC Loadline

-5.9

mΩ

V_TOB_Imax

V_TOB_Imin

-AVP Tolerance

+AVP Tolerance

+Ripple

-Ripple

Icc Max

Load Lin

e