Intel G1620T CM8063701448300 Manuel D’Utilisation
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Codes de produits
CM8063701448300
Integrated Clock
58
Datasheet
5.1
Features
Platform clocking is provided internally by the Integrated Clock logic. No external clock
chips are required for the processor to function. All the required platform clocks are
provided by two crystal inputs: a 25 MHz primary reference for the integrated clock
block and a 32.768 kHz reference for the Real Time Clock (RTC) block.
chips are required for the processor to function. All the required platform clocks are
provided by two crystal inputs: a 25 MHz primary reference for the integrated clock
block and a 32.768 kHz reference for the Real Time Clock (RTC) block.
The different inputs and outputs are listed below.
Table 38. Processor Clock Inputs
Clock Domain
Signal Name
Frequency
Usage/Description
Main ICLK_OSCIN
ICLK_OSCOUT
25 MHz
Reference crystal for the iCLK PLL
RTC
ILB_RTC_X1
ILB_RTC_X2
ILB_RTC_X2
32.768 kHz
RTC crystal I/O for RTC block
LPC
ILB_LPC_CLK[1]
25 MHz
Can be configured as an input to
compensate for board routing delays
through Soft Strap.
Table 39. Processor Clock Outputs (Sheet 1 of 2)
Clock Domain
Signal Name
Frequency
Usage/Description
Memory
DRAM0_CKP/N[2,0]
DRAM1_CKP/N[2,0]
DRAM1_CKP/N[2,0]
533/667 MHz
Drives the Memory ranks 0-1. Data rate
(MT/s) is 2x the clock rate.
Note: The frequency is fused in each
Note: The frequency is fused in each
Processor. It is not possible to support both
frequencies on one Processor.
eMMC
MMC1_CLK
MMC1_45_CLK
MMC1_45_CLK
25-50 MHz
25-200 MHz
25-200 MHz
Clock for eMMC 4.41 devices
Clock for eMMC 4.51 devices
Actual clock can run as low as 400 kHz
Clock for eMMC 4.51 devices
Actual clock can run as low as 400 kHz
during initialization.
SDIO
SD2_CLK
25-50 MHz
Clock for SDIO devices
SD Card
SD3_CLK
25-50 MHz
Clock for SD card devices
SPI
PCU_SPI_CLK
20 MHz,
33 MHz,
50 MHz
Clock for SPI flash
PMIC/COMMS
PMC_SUSCLK[3:0]
32.768 kHz
Pass through clock from RTC oscillator
LPC
ILB_LPC_CLK[0:1]
25 MHz
Provided to devices requiring LPC clock
HDA
HDA_CLK
24 MHz
Serial clock for external HDA codec device
PCI Express
PCIE_CLKN[3:0]
PCIE_CLKP[3:0]
PCIE_CLKP[3:0]
100 MHz
Differential Clocks supplied to external PCI
express devices based on assertion of
PCIE_CLKREQ[3:0]# inputs
HDMI
DDI[1:0]_TXP/N[3]
25-148.5 MHz
Differential clock for HDMI devices
HDMI DDC
DDI[1:0]_DDCCLK
100 kHz
Clock for HDMI DDC devices
VGA DDC
VGA_DDCCLK
100 kHz
Clock for VGA DDC devices
SVID
SVID_CLK
25 MHz
Clock used by voltage regulator
I
2
S
LPE_I2S[2:0]_CLK
12.5 MHz
Continuous serial clock for I
2
S interfaces