Intel E7-8891 v2 CM8063601377422 Manuel D’Utilisation

Codes de produits
CM8063601377422
Page de 504
Reference Number: 329595-002
Intel
®
 Xeon
® 
Processor E7 v2 
2800/4800/8800 Product Family 
Datasheet - Volume Two
March 2014

Table des matière des caractéristiques pour Intel E7-8891 v2 CM8063601377422

  • Page 1Intel® Xeon® Processor E7 v2 2800/4800/8800 Product Family Datasheet - Volume Two March 2014 Reference Number: 329595-002
  • Page 2LINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,...
  • Page 3Contents 1 Overview ................................................................................................................. 17 1.1 Introduction ..................................................................................................... 17 1.2 Terminology ..................................................................................................... 18 1.3 Related Documents ........................................................................................... 21 1.4 State...
  • Page 4 4.6 iMC Interface ....................................................................................................37 4.6.1 HA to MC Interface .................................................................................37 4.6.2 Target Address Decode (TAD)...................................................................37 5 iMC Functional Description...
  • Page 5 7.4.10 Intel SMI2 Half-Width Failover Mode ......................................................... 56 7.4.11 Memory Migration .................................................................................. 57 7.5 IIO RAS ........................................................................................................... 57 7.5.1...
  • Page 6 13.1.6 CCR ......................................................................................................86 13.1.7 CLSR.....................................................................................................86 13.1.8 PLAT .....................................................................................................87 13.1.9 HDR......................................................................................................87 13.1.10BIST .....................................................................................................87 13.1.11SVID.....................................................................................................87 13.1.12SDID ....................................................................................................88 13.1.13CAPPTR .................................................................................................88 13.1.14INTL .....................................................................................................88...
  • Page 7 14.2.15IOLIM ................................................................................................. 203 14.2.16SECSTS .............................................................................................. 204 14.2.17MBAS ................................................................................................. 205 14.2.18MLIM .................................................................................................. 206 14.2.19PBAS .................................................................................................. 206 14.2.20PLIM................................................................................................... 207 14.2.21PBASU ...................................................................................................
  • Page 8 14.2.71ERRCAPHDR......................................................................................... 252 14.2.72UNCERRSTS ......................................................................................... 252 14.2.73UNCERRMSK ........................................................................................ 253 14.2.74UNCERRSEV......................................................................................... 253 14.2.75CORERRSTS......................................................................................... 255 14.2.76CORERRMSK ........................................................................................ 255 14.2.77ERRCAP............................................................................................... 256 14.2.78HDRLOG[0:3]....................................................................................... 256...
  • Page 9 14.3.1 DMIVC0RCAP ....................................................................................... 299 14.3.2 DMIVC0RCTL ....................................................................................... 300 14.3.3 DMIVC0RSTS ....................................................................................... 301 14.3.4 DMIVC1RCAP ....................................................................................... 301 14.3.5 DMIVC1RCTL ..........................................................................................
  • Page 10 14.5.1 CHANCNT ............................................................................................ 334 14.5.2 XFERCAP ............................................................................................. 335 14.5.3 GENCTRL ............................................................................................. 335 14.5.4 INTRCTRL ............................................................................................ 335 14.5.5 ATTNSTATUS ..........................................................................................
  • Page 11 14.6.19MMCFG_LIMIT ..................................................................................... 362 14.6.20TSEG .................................................................................................. 363 14.6.21GENPROTRANGE[1:0]_BASE .................................................................. 363 14.6.22GENPROTRANGE[1:0]_LIMIT ................................................................. 364 14.6.23GENPROTRANGE2_BASE ....................................................................... 364 14.6.24GENPROTRANGE2_LIMIT ....................................................................... 364 14.6.25TOLM.....................................................................................................
  • Page 12 14.7.14VTD[0:1]_PROT_LOW_MEM_BASE .......................................................... 412 14.7.15VTD[0:1]_PROT_LOW_MEM_LIMIT .......................................................... 412 14.7.16VTD[0:1]_PROT_HIGH_MEM_BASE ......................................................... 412 14.7.17VTD[0:1]_PROT_HIGH_MEM_LIMIT ......................................................... 413 14.7.18VTD[0:1]_INV_QUEUE_HEAD ................................................................. 413 14.7.19VTD[0:1]_INV_QUEUE_TAIL................................................................... 413 14.7.20VTD[0:1]_INV_QUEUE_ADD................................................................... 414...
  • Page 13 14.8.39GSYSCTL............................................................................................. 448 14.8.40GFFERRST, GFNERRST .......................................................................... 448 14.8.41GNFERRST, GNNERRST ......................................................................... 449 14.8.42IRPP[0:1]ERRST................................................................................... 449 14.8.43IRPP[0:1]ERRCTL ................................................................................. 450 14.8.44IRPP[0:1]FFERRST, IRPP[0:1]FNERRST ................................................... 451...
  • Page 14 14.10 Device 5 Function 4 I/OxAPIC............................................................................ 489 14.10.1INDEX ................................................................................................. 490 14.10.2WINDOW ............................................................................................. 490 14.10.3EOI..................................................................................................... 490 14.10.4Device 5 Function 4...
  • Page 15Revision History Doc ID Description Date 329595-001 Initial Release February 2014 329595-002 Added Chapters 12 through 15 February 2014 §...
  • Page 1616 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
  • Page 17: 1 OverviewOverview 1 Overview 1.1 Introduction The Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family processors are the next generation of 64-bit,...
  • Page 18 Overview — One Intel® C102/C104 Scalable Memory Buffer per Intel SMI2 channel, with up to two DDR3 channels per...
  • Page 19Overview Table 1-1. Processor Terminology (Sheet 2 of 4) Term Description Functional Operation Refers to the normal operating conditions in...
  • Page 20 Overview Table 1-1. Processor Terminology (Sheet 3 of 4) Term Description MLC Mid Level Cache NCTF Non-Critical to Function:...
  • Page 21Overview Table 1-1. Processor Terminology (Sheet 4 of 4) Term Description Uncore The portion of the processor comprising the shared...
  • Page 22 Overview Table 1-3. Public Specifications (Sheet 2 of 2) Document Document Number/ Location Intel® Trusted Execution Technology Software Development...
  • Page 23: 2 The Processor Architecture OverviewThe Processor Architecture Overview 2 The Processor Architecture Overview This section describes the key architecture features of the core and...
  • Page 24 The Processor Architecture Overview 2.1.1 Frequency The processor cores are designed to run at a rated frequency and the...
  • Page 25The Processor Architecture Overview 2.2 Uncore Features This section describes key features supported by each of the uncore modules designed...
  • Page 26 The Processor Architecture Overview Note that in a 2S configuration, if parallel Intel QPI ports are to be used,...
  • Page 27The Processor Architecture Overview • Home Snoop Protocol Support: The Home Agent implements Intel QPI v1.1 “home snoop protocol” by...
  • Page 28 The Processor Architecture Overview • PCI Express Interfaces: The I/O module incorporates PCI Express interface. The processor can support...
  • Page 29: 3 Cbo Functional DescriptionCbo Functional Description 3 Cbo Functional Description The Intel Xeon processor E7 v2 product family core to the last level...
  • Page 30 Cbo Functional Description 3.2 Source Address Decoder Within the Cbo, requests go through the Source Address Decoder (SAD) at...
  • Page 31Cbo Functional Description 3.2.2.2 IIO Address Decoders Although many of the address ranges for the IIO address decoders are now...
  • Page 32 Cbo Functional Description 3.2.3.1 SAD Decoders and Priority There are a total of four types of decoders in the...
  • Page 33Cbo Functional Description 3.2.6 TSEG Range (CSR_TSEG <= addr) The TSEG range is used to manage the SMM memory region...
  • Page 34 Cbo Functional Description 3.3 Viral Support The Intel Xeon processor E7 v2 product family supports Viral mode of the...
  • Page 35: 4 Home Agent Functional DescriptionHome Agent Functional Description 4 Home Agent Functional Description The Intel Xeon processor E7 v2 product family supports up to...
  • Page 36 Home Agent Functional Description 4.1.3 Intel QPI Home Logic The home logic is responsible for detecting and resolving the...
  • Page 37Home Agent Functional Description 4.6 iMC Interface The HA operates at the same frequency as Cbo in the uncore clock...
  • Page 38 Home Agent Functional Description 38 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014...
  • Page 39: 5 iMC Functional DescriptioniMC Functional Description 5 iMC Functional Description 5.1 Overview The Intel Xeon processor E7 v2 product family implements two internal...
  • Page 40 iMC Functional Description Figure 5-1. Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Memory Interface Processor Riser card M em...
  • Page 41iMC Functional Description In Intel Xeon processor E7 v2 product family channel 0 can be used to control two DDR3...
  • Page 42 iMC Functional Description The memory address decoder supports channel and rank interleaving, several DIMM and DRAM device types, and...
  • Page 43iMC Functional Description Execution of a single refresh is tRFC, and it takes 110 – 350 ns according to DDR3...
  • Page 44 iMC Functional Description 44 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
  • Page 45: 6 IIO Functional DescriptionIIO Functional Description 6 IIO Functional Description 6.1 Integrated I/O Module Overview The IIO module provides: • x32 PCI Express...
  • Page 46 IIO Functional Description • 2.5 GHz (1.0) and 5 GHz (2.0) and 8 GHz (3.0) • Full peer-to-peer support...
  • Page 47IIO Functional Description 6.2 PECI and JTAG 6.2.1 PECI PECI provides access to both DMI and PCIe CSRs. 6.2.2 JTAG...
  • Page 48 IIO Functional Description Figure 6-2. PCI Express Lane Partitioning Port 0 Port 2 Port 3 DMI / PCIe PCIe...
  • Page 49IIO Functional Description 6.3.4 Technologies Supported over PCI Express 6.3.4.1 3.0 Protocol Enhancements Supported enhancements are • Transaction Processing Hints...
  • Page 50 IIO Functional Description 50 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
  • Page 51: 7 Reliability, Availability, Serviceability, and ManageabilityReliability, Availability, Serviceability, and Manageability 7 Reliability, Availability, Serviceability, and Manageability This chapter describes RASM (Reliability, Availability, Serviceability and Manageability)...
  • Page 52 Reliability, Availability, Serviceability, and Manageability 7.1.1 Error Sources In general two kinds of errors could occur in a system...
  • Page 53Reliability, Availability, Serviceability, and Manageability mode all the UC errors are reported as ‘Fatal’, and lead to MCE1 (Machine Check...
  • Page 54 Reliability, Availability, Serviceability, and Manageability Several of the RASM features require BIOS/SMM and SW1 support. Therefore, system architects implementing...
  • Page 55Reliability, Availability, Serviceability, and Manageability The expectation is that a system cold reset must be performed when a fatal error/viral...
  • Page 56 Reliability, Availability, Serviceability, and Manageability 7.4.4.2 Rank Sparing 7.4.4.2.1 Usage Rank sparing enables a failing rank to be replaced...
  • Page 57Reliability, Availability, Serviceability, and Manageability 7.4.11 Memory Migration The Intel Xeon processor E7 v2 product family will provide support for...
  • Page 58 Reliability, Availability, Serviceability, and Manageability 7.5.2.1.3 Fatal Errors (Severity 2 Error) Fatal errors are uncorrectable error conditions which render...
  • Page 59Reliability, Availability, Serviceability, and Manageability 7.5.3.3.1 PCIe Error Severity Mapping PCIe errors can be classified as two types: Uncorrectable errors...
  • Page 60 Reliability, Availability, Serviceability, and Manageability 60 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February...
  • Page 61: 8 Reset FlowReset Flow 8 Reset Flow This chapter describes the reset flow for the Intel Xeon processor E7 v2 product family...
  • Page 62 Reset Flow 62 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
  • Page 63: 9 Ubox Functional DescriptionUbox Functional Description 9 Ubox Functional Description 9.1 Ubox Overview The UBOX is the piece of logic that deals with...
  • Page 64 Ubox Functional Description 9.4.2 TAP Access The TAP port into the socket will be a master on the message...
  • Page 65: 10 PCU Functional DescriptionPCU Functional Description 10 PCU Functional Description This chapter describes the PCU module features along with PECI interfaces in more...
  • Page 66 PCU Functional Description Figure 10-1. Power and Thermal Management Architecture Overview 10.2 Platform Environment Control Interface (PECI) The Platform...
  • Page 67PCU Functional Description — Note that platform ‘power’ management includes monitoring and control for both the processor and DRAM subsystem...
  • Page 68 PCU Functional Description many operating conditions under which one or more cores in the processor would be capable of...
  • Page 69: 11 Performance MonitoringPerformance Monitoring 11 Performance Monitoring This chapter will provide an overview of the Intel Xeon processor E7 v2 product family...
  • Page 70 Performance Monitoring 70 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
  • Page 71: 12 Registers Overview and Configuration ProcessRegisters Overview and Configuration Process 12 Registers Overview and Configuration Process This volume of the Intel® Xeon® Processor E7-2800/4800/8800 v2...
  • Page 72 Registers Overview and Configuration Process Figure 12-1. Processor integrated I/O device map Processor Integrated I/O Core (Device 5) Memory...
  • Page 73Registers Overview and Configuration Process 12.1.2 Processor Uncore Devices (CPUBUSNO (1)) The configuration registers for these devices are mapped as...
  • Page 74 Registers Overview and Configuration Process • PCI Configuration Registers (CSRs): CSRs are chipset specific registers that are located in...
  • Page 75Registers Overview and Configuration Process Table 12-1. Functions specifically handled by the processor (Sheet 1 of 3) Register Group DID...
  • Page 76 Registers Overview and Configuration Process Table 12-1. Functions specifically handled by the processor (Sheet 2 of 3) Register Group...
  • Page 77Registers Overview and Configuration Process Table 12-1. Functions specifically handled by the processor (Sheet 3 of 3) Register Group DID...
  • Page 78 Registers Overview and Configuration Process • Devices that are hidden from host configuration space via the DEVHIDE register are...
  • Page 79Registers Overview and Configuration Process 12.2.2 MSR Access Machine Specific Registers are architectural and accessed by using specific ReadMSR/WriteMSR instructions....
  • Page 80 Registers Overview and Configuration Process Table 12-3. Register attribute definitions (Sheet 2 of 2) Attribute Description RW_LB Read/Write Lock...
  • Page 81Registers Overview and Configuration Process 12.4 Notational Conventions 12.4.1 Socket ID In cases where the target is only 3 bits,...
  • Page 82 Registers Overview and Configuration Process 82 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February...
  • Page 83: 13 Processor Uncore Configuration RegistersProcessor Uncore Configuration Registers 13 Processor Uncore Configuration Registers This chapter contains the Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family...
  • Page 84 Processor Uncore Configuration Registers 13.1.2 DID Type: CFG PortID: N/A Bus: 1 Offset: 0x2 Device Identification Number (device_identification_number): 15:0...
  • Page 85Processor Uncore Configuration Registers 13.1.4 PCISTS Type: CFG PortID: N/A Bus: 1 Offset: 0x6 Bit Attr Default Description Detected Parity...
  • Page 86 Processor Uncore Configuration Registers 13.1.5 RID Type: CFG PortID: N/A Bus: 1 Offset: 0x8 Bit Attr Default Description revision_id:...
  • Page 87Processor Uncore Configuration Registers 13.1.8 PLAT Type: CFG PortID: N/A Bus: 1 Offset: 0xd Bit Attr Default Description Primary Latency...
  • Page 88 Processor Uncore Configuration Registers 13.1.12 SDID Type: CFG PortID: N/A Bus: 1 Offset: 0x2e Bit Attr Default Description Subsystem...
  • Page 89Processor Uncore Configuration Registers 13.1.16 MINGNT Type: CFG PortID: N/A Bus: 1 Offset: 0x3e Bit Attr Default Description Minimum Grant...
  • Page 90 Processor Uncore Configuration Registers Bus Device Function Memory Channel Comments 6 Memory Channel 0 7 Memory Channel 1 1...
  • Page 91Processor Uncore Configuration Registers Register name Offset Size MCMTR2 0xb0 32 MC_INIT_STATE_G 0xb4 32 RCOMP_TIMER 0xc0 32 PXPENHCAP 0x100 32...
  • Page 92 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function:...
  • Page 93Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function: 0...
  • Page 94 Processor Uncore Configuration Registers For 1-way interleave, channel 1-3 mirror pair: target list = <1,3,x,x>, TAD ways = “00”...
  • Page 95Processor Uncore Configuration Registers 13.2.1.4 MCMTR2 MC Memory Technology Register 2 Type: CFG PortID: N/A Bus: 1 Device: 15 Function:...
  • Page 96 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function:...
  • Page 97Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function: 0...
  • Page 98 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function:...
  • Page 99Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function: 0...
  • Page 100 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function:...
  • Page 101Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function: 0...
  • Page 102 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function:...
  • Page 103Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function: 0...
  • Page 104 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function:...
  • Page 105Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function: 0...
  • Page 106 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function:...
  • Page 107Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function: 0...
  • Page 108 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0 Bus: 1 Device: 29 Function:...
  • Page 109Processor Uncore Configuration Registers 13.2.1.19 SMB_PERIOD_CFG SMBus Clock Period Config. Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 0...
  • Page 110 Processor Uncore Configuration Registers 13.2.2 Device 15, 29 Function 1 The Device 15 and 29 Function 1 contain the...
  • Page 111Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 1 Bus: 1 Device: 29 Function: 1...
  • Page 112 Processor Uncore Configuration Registers 13.2.2.3 SPARECTL Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 1 Bus: 1 Device:...
  • Page 113Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 1 Bus: 1 Device: 29 Function: 1...
  • Page 114 Processor Uncore Configuration Registers 13.2.2.5 SCRUBADDRESSLO Scrub Address Low. This register contains part of the address of the last...
  • Page 115Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 1 Bus: 1 Device: 29 Function: 1...
  • Page 116 Processor Uncore Configuration Registers 13.2.2.8 SPAREINTERVAL Defines the interval between normal and sparing operations. Interval is defined in dclk....
  • Page 117Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 1 Bus: 1 Device: 29 Function: 1...
  • Page 118 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 1 Bus: 1 Device: 29 Function:...
  • Page 119Processor Uncore Configuration Registers 13.2.2.13 LEAKY_BUCKET_CNTR_HI Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 1 Bus: 1 Device: 29...
  • Page 120 Processor Uncore Configuration Registers Register name Offset Size DIMMMTR_2 0x88 32 PXPENHCAP 0x100 32 13.2.3.1 PXPCAP Type: CFG PortID:...
  • Page 121Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 2,3,4,5 Bus: 1 Device: 29 Function: 2,3,4,5...
  • Page 122 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 15 Function: 2,3,4,5 Bus: 1 Device: 29 Function:...
  • Page 123Processor Uncore Configuration Registers Register Name Offset Size PCICMD 0x4 16 PCISTS 0x6 16 RID 0x8 8 CCR 0x9 24...
  • Page 124 Processor Uncore Configuration Registers Register Name Offset Size PCICMD 0x4 16 PCISTS 0x6 16 RID 0x8 8 CCR 0x9...
  • Page 125Processor Uncore Configuration Registers Register Name Offset Size DIMM_TEMP_EV_OFST_2 0x148 32 DIMMTEMPSTAT_0 0x150 32 DIMMTEMPSTAT_1 0x154 32 DIMMTEMPSTAT_2 0x158 32...
  • Page 126 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 127Processor Uncore Configuration Registers 13.2.4.4 PMONCNTRCFG_[0:4] Perfmon Counter Control Register Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5...
  • Page 128 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 129Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function: 0,1,4,5...
  • Page 130 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 131Processor Uncore Configuration Registers 13.2.4.9 CHN_TEMP_STAT Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30...
  • Page 132 Processor Uncore Configuration Registers 13.2.4.11 DIMM_TEMP_TH_[0:2] Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device:...
  • Page 133Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function: 0,1,4,5...
  • Page 134 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 135Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function: 0,1,4,5...
  • Page 136 Processor Uncore Configuration Registers 13.2.4.16 TCDBP Timing Constraints DDR3 Bin Parameter. Type: CFG PortID: N/A Bus: 1 Device: 16...
  • Page 137Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30Function:0,1,4,5 Offset: 0x204...
  • Page 138 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 139Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function: 0,1,4,5...
  • Page 140 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 141Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function: 0,1,4,5...
  • Page 142 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 143Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function: 0,1,4,5...
  • Page 144 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 145Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function: 0,1,4,5...
  • Page 146 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30 Function:...
  • Page 147Processor Uncore Configuration Registers 13.2.4.31 TCMRS Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 0,1,4,5 Bus: 1 Device: 30...
  • Page 148 Processor Uncore Configuration Registers Register Name Offset Size Functions SVID 0x2c 16 2,3,6,7 SDID 0x2e 16 2,3,6,7 CAPPTR 0x34...
  • Page 149Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 2,3,6,7 Bus: 1 Device: 30 Function: 2,3,6,7...
  • Page 150 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 2,3,6,7 Bus: 1 Device: 30 Function:...
  • Page 151Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 2,3,6,7 Bus: 1 Device: 30 Function: 2,3,6,7...
  • Page 152 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 2,3,6,7 Bus: 1 Device: 30 Function:...
  • Page 153Processor Uncore Configuration Registers 13.2.5.10 CORRERRTHRSHLD_3 This register holds the per rank corrected error thresholding value. Type: CFG PortID: N/A...
  • Page 154 Processor Uncore Configuration Registers 13.2.5.12 LEAKY_BKT_2ND_CNTR_REG Type: CFG PortID: N/A Bus: 1 Device: 16 Function: 2,3,6,7 Bus: 1 Device:...
  • Page 155Processor Uncore Configuration Registers For lock-step channel configuration, only one x8 device can be tagged per rank-pair. SMM software must...
  • Page 156 Processor Uncore Configuration Registers Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family has two Home Agents: HA0 and HA1. Device...
  • Page 157Processor Uncore Configuration Registers 13.4 PCIe* Ring Interface (R2PCIE) Registers 13.4.1 Device 19 Function 0 Register name Offset Size VID...
  • Page 158 Processor Uncore Configuration Registers Register name Offset Size Device CAPPTR 0x34 8 8, 9, 24 INTL 0x3c 8 8,...
  • Page 159Processor Uncore Configuration Registers Register name Offset Size MINGNT 0x3e 8 MAXLAT 0x3f 8 PXPCAP 0x40 32 PXPENHCAP 0x100 32...
  • Page 160 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 8 Function: 4 Bus: 1 Device: 9 Function:...
  • Page 161Processor Uncore Configuration Registers 13.6.1 Device 11 Function 0 Register name Offset Size VID 0x0 16 DID 0x2 16 PCICMD...
  • Page 162 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 11 Function: 0 Offset: 0x40 Bit Attr Default...
  • Page 163Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 11 Function: 0 Offset: 0x48 Bit Attr Default Description...
  • Page 164 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 11 Function: 0 Offset: 0x54 Bit Attr Default...
  • Page 165Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 11 Function: 0 Offset: 0x64 Bit Attr Default Description...
  • Page 166 Processor Uncore Configuration Registers 13.6.3 Device 11 Function 3 Register name Offset Size VID 0x0 16 DID 0x2 16...
  • Page 167Processor Uncore Configuration Registers 13.6.3.2 SMICTRL SMI generation control. Type: CFG PortID: N/A Bus: 1 Device: 11 Function: 3 Offset:...
  • Page 168 Processor Uncore Configuration Registers Register name Offset Size PCISTS 0x6 16 RID 0x8 8 CCR 0x9 24 CLSR 0xc...
  • Page 169Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 0 Offset: 0x60 Bit Attr Default Description...
  • Page 170 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 0 Offset: 0x84 Bit Attr Default...
  • Page 171Processor Uncore Configuration Registers The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT]. The data is updated...
  • Page 172 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 0 Offset: 0xe4 Bit Attr Default...
  • Page 173Processor Uncore Configuration Registers 13.7.2.1 SSKPD Sticky Scratchpad Data. This register holds 64 writable bits with no functionality behind them....
  • Page 174 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 1 Offset: 0xa4 Bit Attr Default...
  • Page 175Processor Uncore Configuration Registers 13.7.3.1 PACKAGE_RAPL_PERF_STATUS This register is used by PCU microcode to report Package Power limit violations in...
  • Page 176 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 2 Offset: 0x90 Bit Attr Default...
  • Page 177Processor Uncore Configuration Registers Dual mapped as PCU IOREG Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 2 Offset:...
  • Page 178 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 2 Offset: 0xf8 Bit Attr Default...
  • Page 179Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 3 Offset: 0x80 Bit Attr Default Description...
  • Page 180 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 3 Offset: 0x84 Bit Attr Default...
  • Page 181Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 3 Offset: 0x84 Bit Attr Default Description...
  • Page 182 Processor Uncore Configuration Registers 13.7.4.3 CAPID1 This register is a Capability Register used to expose enable/disable BIOS use. Type:...
  • Page 183Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 3 Offset: 0x88 Bit Attr Default Description...
  • Page 184 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 3 Offset: 0x8c Bit Attr Default...
  • Page 185Processor Uncore Configuration Registers 13.7.4.5 CAPID3 This register is a Capability Register used to expose enable/disable features for BIOS. Type:...
  • Page 186 Processor Uncore Configuration Registers Type: CFG PortID: N/A Bus: 1 Device: 10 Function: 3 Offset: 0x90 Bit Attr Default...
  • Page 187Processor Uncore Configuration Registers 13.7.4.6 CAPID4 This register is a Capability Register used to expose enable/disable for BIOS use. Type:...
  • Page 188 Processor Uncore Configuration Registers 188 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014...
  • Page 189: 14 Integrated I/O (IIO) Configuration RegistersIntegrated I/O (IIO) Configuration Registers 14 Integrated I/O (IIO) Configuration Registers 14.1 Registers Overview 14.1.1 Configuration Registers (CSR) There are...
  • Page 190 Integrated I/O (IIO) Configuration Registers 14.1.4 PCI Vs. PCIe* Device / Function PCI devices/functions do NOT have a PCIe*...
  • Page 191Integrated I/O (IIO) Configuration Registers Device 0 Device 2 Device 3 Register name Offset Size function function function RID 0x8...
  • Page 192 Integrated I/O (IIO) Configuration Registers Device 0 Device 2 Device 3 Register name Offset Size function function function DEVSTS...
  • Page 193Integrated I/O (IIO) Configuration Registers Device 0 Device 2 Device 3 Register name Offset Size function function function HDRLOG2 0x16c...
  • Page 194 Integrated I/O (IIO) Configuration Registers Device 0 Device 2 Device 3 Register name Offset Size function function function LN10EQ...
  • Page 195Integrated I/O (IIO) Configuration Registers 14.2.2 DID Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus:...
  • Page 196 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 197Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 198 Integrated I/O (IIO) Configuration Registers 14.2.4 PCISTS Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3...
  • Page 199Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 200 Integrated I/O (IIO) Configuration Registers 14.2.5 RID Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3...
  • Page 201Integrated I/O (IIO) Configuration Registers 14.2.8 PLAT Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus:...
  • Page 202 Integrated I/O (IIO) Configuration Registers 14.2.11 PBUS Primary Bus Number Register. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0...
  • Page 203Integrated I/O (IIO) Configuration Registers 14.2.14 IOBAS I/O Base Register. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode)...
  • Page 204 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3...
  • Page 205Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3 Bus:...
  • Page 206 Integrated I/O (IIO) Configuration Registers 14.2.18 MLIM Memory Limit Register. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe*...
  • Page 207Integrated I/O (IIO) Configuration Registers 14.2.20 PLIM Prefetchable Memory Limit Register. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe*...
  • Page 208 Integrated I/O (IIO) Configuration Registers 14.2.22 PLIMU Prefetchable Memory Limit Upper 32 bits. Type: CFG PortID: N/A Bus: 0...
  • Page 209Integrated I/O (IIO) Configuration Registers 14.2.24 INTL Interrupt Line Register. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0...
  • Page 210 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3...
  • Page 211Integrated I/O (IIO) Configuration Registers 14.2.27 SCAPID Subsystem Capability Identity. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode)...
  • Page 212 Integrated I/O (IIO) Configuration Registers 14.2.30 SDID Subsystem Identity. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2 Mode)...
  • Page 213Integrated I/O (IIO) Configuration Registers 14.2.32 MSICAPID MSI Capability ID. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode)...
  • Page 214 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3...
  • Page 215Integrated I/O (IIO) Configuration Registers 14.2.36 MSGDAT MSI Data Register. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode)...
  • Page 216 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3...
  • Page 217Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 218 Integrated I/O (IIO) Configuration Registers 14.2.42 DEVCAP The PCI Express Device Capabilities register identifies device specific information for the...
  • Page 219Integrated I/O (IIO) Configuration Registers 14.2.43 DEVCTRL PCI Express Device Control. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2...
  • Page 220 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2 Mode) Offset: 0xf0 Bus: 0...
  • Page 221Integrated I/O (IIO) Configuration Registers 14.2.44 DEVSTS PCI Express Device Status. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2...
  • Page 222 Integrated I/O (IIO) Configuration Registers 14.2.45 LNKCAP PCI Express Link Capabilities The Link Capabilities register identifies the PCI Express...
  • Page 223Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 224 Integrated I/O (IIO) Configuration Registers 14.2.46 LNKCON PCI Express Link Control The PCI Express Link Control register controls the...
  • Page 225Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2 Mode) Offset: 0x1b0 Bus: 0 Device:...
  • Page 226 Integrated I/O (IIO) Configuration Registers 14.2.47 LNKSTS PCI Express Link Status The PCI Express Link Status register provides information...
  • Page 227Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2 Mode) Offset: 0x1b2 Bus: 0 Device:...
  • Page 228 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3...
  • Page 229Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3 Bus:...
  • Page 230 Integrated I/O (IIO) Configuration Registers 14.2.49 SLTCON PCI Express Slot Control. Any write to this register will set the...
  • Page 231Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3 Bus:...
  • Page 232 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3...
  • Page 233Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3 Bus:...
  • Page 234 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 235Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 236 Integrated I/O (IIO) Configuration Registers 14.2.52 ROOTCAP PCI Express Root Capabilities. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0...
  • Page 237Integrated I/O (IIO) Configuration Registers 14.2.54 DEVCAP2 PCI Express Device Capabilities 2 Register. Type: CFG PortID: N/A Bus: 0 Device:...
  • Page 238 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 239Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2 Mode) Offset: 0xf8 Bus: 0 Device:...
  • Page 240 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 241Integrated I/O (IIO) Configuration Registers 14.2.57 LNKCON2 Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2 Mode) Offset: 0x1c0 Bus:...
  • Page 242 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2 Mode) Offset: 0x1c0 Bus: 0...
  • Page 243Integrated I/O (IIO) Configuration Registers 14.2.58 LNKSTS2 PCI Express Link Status Register 2. Type: CFG PortID: N/A Bus: 0 Device:...
  • Page 244 Integrated I/O (IIO) Configuration Registers 14.2.59 PMCAP Power Management Capabilities The PM Capabilities Register defines the capability ID, next...
  • Page 245Integrated I/O (IIO) Configuration Registers 14.2.60 PMCSR Power Management Control and Status Register This register provides status and control information...
  • Page 246 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 247Integrated I/O (IIO) Configuration Registers 14.2.62 XPREUT_HDR_CAP REUT PCIe* Header Capability. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus:...
  • Page 248 Integrated I/O (IIO) Configuration Registers 14.2.64 ACSCAPHDR Access Control Services Extended Capability Header. Type: CFG PortID: N/A Bus: 0...
  • Page 249Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* mode) Bus: 0 Device: 2Function:0-3 Bus:...
  • Page 250 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (PCIe* Mode) Bus: 0 Device: 2Function:0-3...
  • Page 251Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 252 Integrated I/O (IIO) Configuration Registers 14.2.71 ERRCAPHDR PCI Express Enhanced Capability Header - Root Ports. Type: CFG PortID: N/A...
  • Page 253Integrated I/O (IIO) Configuration Registers 14.2.73 UNCERRMSK Uncorrectable Error Mask. This register masks uncorrectable errors from being signaled. Type: CFG...
  • Page 254 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 255Integrated I/O (IIO) Configuration Registers 14.2.75 CORERRSTS Correctable Error Status. This register identifies the status of the correctable errors that...
  • Page 256 Integrated I/O (IIO) Configuration Registers 14.2.77 ERRCAP Advanced Error capabilities and Control Register. Type: CFG PortID: N/A Bus: 0...
  • Page 257Integrated I/O (IIO) Configuration Registers This register controls behavior upon detection of errors. Type: CFG PortID: N/A Bus: 0 Device:...
  • Page 258 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 259Integrated I/O (IIO) Configuration Registers 14.2.82 PERFCTRLSTS_0 Performance Control and Status Register 0. Type: CFG PortID: N/A Bus: 0 Device:...
  • Page 260 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 261Integrated I/O (IIO) Configuration Registers 14.2.84 MISCCTRLSTS_0 MISC Control and Status Register 0. Type: CFG PortID: N/A Bus: 0 Device:...
  • Page 262 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 263Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 264 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0...
  • Page 265Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 266 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0 Bus: 0...
  • Page 267Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 (DMI2 Mode) Offset: 0x1a0 Bit Attr Default...
  • Page 268 Integrated I/O (IIO) Configuration Registers 14.2.90 ERRINJHDR PCI Express Error Injection Capability Header. Type: CFG PortID: N/A Bus: 0...
  • Page 269Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 270 Integrated I/O (IIO) Configuration Registers the system software. Mask bits mask the reporting of an error and severity bit...
  • Page 271Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 272 Integrated I/O (IIO) Configuration Registers 14.2.97 XPUNCERRSEV XP Uncorrectable Error Severity Type: CFG PortID: N/A Bus: 0 Device: 0Function:0...
  • Page 273Integrated I/O (IIO) Configuration Registers This register masks PCIe* link related uncorrectable errors from causing the associated AER status bit...
  • Page 274 Integrated I/O (IIO) Configuration Registers 14.2.101 RPEDMASK Root Port Error Detect Status Mask This register masks the associated error...
  • Page 275Integrated I/O (IIO) Configuration Registers 14.2.103 XPCOREDMASK XP Correctable Error Detect Mask This register masks other correctable errors from causing...
  • Page 276 Integrated I/O (IIO) Configuration Registers Check that the perfmon registers are per “cluster”. Type: CFG PortID: N/A Bus: 0...
  • Page 277Integrated I/O (IIO) Configuration Registers 14.2.107 LNKCON3 Link Control 3 Register. Type: CFG PortID: N/A Bus: 0 Device: 2Function:0-3 Bus:...
  • Page 278 Integrated I/O (IIO) Configuration Registers 14.2.109 LN[0:3]EQ Lane 0 through Lane 3 Equalization Control Type: CFG PortID: N/A Bus:...
  • Page 279Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 2Function:0-3 Bus: 0 Device: 3Function:0-3 Offset: 0x25c, 0x25e,...
  • Page 280 Integrated I/O (IIO) Configuration Registers 14.2.110 LN[4:7]EQ Lane 4 through Lane 7 Equalization Control This register is unused when...
  • Page 281Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 2Function:0, 2 Bus: 0 Device: 3Function:0, 2 Offset:...
  • Page 282 Integrated I/O (IIO) Configuration Registers 14.2.111 LN[8:15]EQ Lane 8 though Lane 15 Equalization Control This register is unused when...
  • Page 283Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 2Function:0 Bus: 0 Device: 3Function:0 Offset: 0x26c, 0x26e,...
  • Page 284 Integrated I/O (IIO) Configuration Registers 14.2.112 LER_CAP Live Error Recovery Capability. Type: CFG PortID: N/A Bus: 0 Device: 0Function:0...
  • Page 285Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0-3 Bus: 0 Device:...
  • Page 286 Integrated I/O (IIO) Configuration Registers 14.2.115 LER_UNCERRMSK Live Error Recovery Uncorrectable Error Mask This register masks uncorrectable errors from...
  • Page 287Integrated I/O (IIO) Configuration Registers 14.2.116 LER_XPUNCERRMSK Live Error Recovery XP Uncorrectable Error Mask. Type: CFG PortID: N/A Bus: 0...
  • Page 288 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0 Bus: 0...
  • Page 289Integrated I/O (IIO) Configuration Registers 14.2.119 XPPMCL[0:1] XP PM Compare Low Bits The value of PMD is compared to the...
  • Page 290 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0 Bus: 0...
  • Page 291Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0 Bus: 0 Device:...
  • Page 292 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0 Bus: 0...
  • Page 293Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0 Bus: 0 Device:...
  • Page 294 Integrated I/O (IIO) Configuration Registers IO_Cfg_Write_event = (REQCMP[0] & CMPR[1] & RDWR[1] & DATALEN & (TTYP[2] + (TTYP[1] &...
  • Page 295Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0 Bus: 0 Device:...
  • Page 296 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 0Function:0 Bus: 0 Device: 2Function:0 Bus: 0...
  • Page 297Integrated I/O (IIO) Configuration Registers 14.2.124 XPPMEVH[0:1] XP PM Events High Selections in this register correspond to fields within the...
  • Page 298 Integrated I/O (IIO) Configuration Registers 14.2.125 XPPMER[0:1] XP PM Resource Event. This register is used to select queuing structures...
  • Page 299Integrated I/O (IIO) Configuration Registers 14.3 Device 0 Function 0 Region DMIRCBAR DMI Root Complex Registers Block (RCRB). This block...
  • Page 300 Integrated I/O (IIO) Configuration Registers 14.3.2 DMIVC0RCTL DMI VC0 Resource Control Controls the resources associated with PCI Express Virtual...
  • Page 301Integrated I/O (IIO) Configuration Registers 14.3.3 DMIVC0RSTS DMI VC0 Resource Status. Reports the Virtual Channel specific status. Type: MEM PortID:...
  • Page 302 Integrated I/O (IIO) Configuration Registers 14.3.5 DMIVC1RCTL DMI VC1 Resource Control Controls the resources associated with PCI Express Virtual...
  • Page 303Integrated I/O (IIO) Configuration Registers 14.3.6 DMIVC1RSTS DMI VC1 Resource Status Reports the Virtual Channel specific status. Type: MEM PortID:...
  • Page 304 Integrated I/O (IIO) Configuration Registers 14.3.8 DMIVCPRCTL DMI VCP Resource Control Controls the resources associated with the DMI Private...
  • Page 305Integrated I/O (IIO) Configuration Registers 14.3.9 DMIVCPRSTS DMI VCP Resource Status Reports the Virtual Channel specific status. Type: MEM PortID:...
  • Page 306 Integrated I/O (IIO) Configuration Registers 14.3.11 DMIVCMRCTL DMI VCM Resource Control Controls the resources associated with PCI Express Virtual...
  • Page 307Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 0Function:0 Offset: 0x3e Bit Attr Default Description vcmnp:...
  • Page 308 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 0Function:0 Offset: 0x64 Bit Attr Default Description...
  • Page 309Integrated I/O (IIO) Configuration Registers 14.4 Device 4 Function 0-7 Intel® Quick Data DMA Registers. Register name Offset Size Function...
  • Page 310 Integrated I/O (IIO) Configuration Registers 14.4.1 VID Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x0 Bit Attr...
  • Page 311Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x4 Bit Attr Default Description idsel_stepping_wait_cycle_control:...
  • Page 312 Integrated I/O (IIO) Configuration Registers 14.4.4 PCISTS Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x6 Bit Attr...
  • Page 313Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x6 Bit Attr Default Description intxsts:...
  • Page 314 Integrated I/O (IIO) Configuration Registers 14.4.7 CLSR Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0xc Bit Attr...
  • Page 315Integrated I/O (IIO) Configuration Registers 14.4.8 HDR Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0xe Bit Attr Default...
  • Page 316 Integrated I/O (IIO) Configuration Registers 14.4.10 SVID Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x2c Bit Attr...
  • Page 317Integrated I/O (IIO) Configuration Registers 14.4.14 INTPIN Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x3d Bit Attr Default...
  • Page 318 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0 Offset: 0x60 Bit Attr Default Description...
  • Page 319Integrated I/O (IIO) Configuration Registers 14.4.18 MSIXMSGCTL MSI-X Message Control. Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x82...
  • Page 320 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x88 Bit Attr Default Description...
  • Page 321Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x92 Bit Attr Default Description device_port_type:...
  • Page 322 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x94 Bit Attr Default Description...
  • Page 323Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x98 Bit Attr Default Description fatal_error_reporting_enable:...
  • Page 324 Integrated I/O (IIO) Configuration Registers 14.4.27 DEVCAP2 Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0xb4 Bit Attr...
  • Page 325Integrated I/O (IIO) Configuration Registers 14.4.29 PMCAP Power Management Capability. The PM Capabilities Register defines the capability ID, next pointer...
  • Page 326 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0xe4 Bit Attr Default Description...
  • Page 327Integrated I/O (IIO) Configuration Registers 14.4.31 DMAUNCERRSTS DMA Cluster Uncorrectable Error Status. Type: CFG PortID: N/A Bus: 0 Device: 4Function:0...
  • Page 328 Integrated I/O (IIO) Configuration Registers This register controls severity of uncorrectable DMA unit errors between fatal and non- fatal....
  • Page 329Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0 Offset: 0x160 Bit Attr Default Description global_error_pointer:...
  • Page 330 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x180 Bit Attr Default Description...
  • Page 331Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x180 Bit Attr Default Description descriptor_error:...
  • Page 332 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset: 0x184 Bit Attr Default Description...
  • Page 333Integrated I/O (IIO) Configuration Registers 14.4.39 CHANERRPTR DMA Channel Error Pointer. Type: CFG PortID: N/A Bus: 0 Device: 4Function:0-7 Offset:...
  • Page 334 Integrated I/O (IIO) Configuration Registers Register name Offset Size CHANERRMSK 0xac 32 DCACTRL 0xb0 32 DCA_VER 0x100 8 DCA_REQID_OFFSET...
  • Page 335Integrated I/O (IIO) Configuration Registers 14.5.2 XFERCAP Transfer Capacity. The Transfer Capacity specifies the minimum of the maximum DMA transfer...
  • Page 336 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0x3 Bit Attr Default Description...
  • Page 337Integrated I/O (IIO) Configuration Registers 14.5.7 INTRDELAY Interrupt Delay. Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0xc Bit...
  • Page 338 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0x10 Bit Attr Default Description...
  • Page 339Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0x10 Bit Attr Default Description xor:...
  • Page 340 Integrated I/O (IIO) Configuration Registers 14.5.11 CBPRIO Intel® Quick Data DMA Priority Register. Type: MEM PortID: 8’h7e Bus: 0...
  • Page 341Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0x80 Bit Attr Default Description anyerr_abrt_en:...
  • Page 342 Integrated I/O (IIO) Configuration Registers Setting more than one of these bits with the same write operation will result...
  • Page 343Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0x88 Bit Attr Default Description cmpdscaddr:...
  • Page 344 Integrated I/O (IIO) Configuration Registers 14.5.17 CHANSTS_1 Channel Status 1 Register. The Channel Status Register records the address of...
  • Page 345Integrated I/O (IIO) Configuration Registers 14.5.20 CHANCMP_0 Channel Completion Address 0 Register. This register specifies the address where the DMA...
  • Page 346 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0xa8 Bit Attr Default Description...
  • Page 347Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0xa8 Bit Attr Default Description cdata_parerr:...
  • Page 348 Integrated I/O (IIO) Configuration Registers 14.5.23 CHANERRMSK Channel Error Mask Register. Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7...
  • Page 349Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0x100 Bit Attr Default Description 3:0...
  • Page 350 Integrated I/O (IIO) Configuration Registers 14.5.29 QPI_CAP_ENABLE Intel® QPI Capability Enable Register. Type: MEM PortID: 8’h7e Bus: 0 Device:...
  • Page 351Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0x110 Bit Attr Default Description tag_map_4:...
  • Page 352 Integrated I/O (IIO) Configuration Registers 14.5.32 DCA_REQID[0:1] Global DCA Requester ID Table Registers. Type: MEM PortID: 8’h7e Bus: 0...
  • Page 353Integrated I/O (IIO) Configuration Registers 14.5.34 MSGUPADDR MSI-X Upper Address Registers. Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset:...
  • Page 354 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 4Function:0-7 Offset: 0x3000 Bit Attr Default Description...
  • Page 355Integrated I/O (IIO) Configuration Registers Register name Offset Size GENPROTRANGE1_BASE 0xb0 64 GENPROTRANGE1_LIMIT 0xb8 64 GENPROTRANGE2_BASE 0xc0 64 GENPROTRANGE2_LIMIT 0xc8...
  • Page 356 Integrated I/O (IIO) Configuration Registers Register name Offset Size IRPEGCREDITS 0x840 64 IRP_MISC_DFX2 0x850 32 IRP_MISC_DFX3 0x854 32 14.6.1...
  • Page 357Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x4 Bit Attr Default Description vga_palette_snoop_enable:...
  • Page 358 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x6 Bit Attr Default Description...
  • Page 359Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x9 Bit Attr Default Description sub_class:...
  • Page 360 Integrated I/O (IIO) Configuration Registers 14.6.10 SDID Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x2e Bit Attr...
  • Page 361Integrated I/O (IIO) Configuration Registers 14.6.14 PXPCAPID Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x40 Bit Attr Default...
  • Page 362 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x80 Bit Attr Default Description...
  • Page 363Integrated I/O (IIO) Configuration Registers 14.6.20 TSEG Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0xa8 Bit Attr Default...
  • Page 364 Integrated I/O (IIO) Configuration Registers 14.6.22 GENPROTRANGE[1:0]_LIMIT Generic Protected Memory Range X Limit Address. (X = 1, 0) Type:...
  • Page 365Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0xc8 Bit Attr Default Description 63:51...
  • Page 366 Integrated I/O (IIO) Configuration Registers 14.6.27 NCMEM_BASE Noncoherent Memory Base Address. Type: CFG PortID: N/A Bus: 0 Device: 5Function:0...
  • Page 367Integrated I/O (IIO) Configuration Registers 14.6.29 MENCMEM_BASE Intel® Management Engine (Intel® ME) noncoherent memory base address. Type: CFG PortID: N/A...
  • Page 368 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x108 Bit Attr Default Description...
  • Page 369Integrated I/O (IIO) Configuration Registers 14.6.34 LMMIOH_BASE Local MMIO High Base. Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset:...
  • Page 370 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x140 Bit Attr Default Description...
  • Page 371Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x140 Bit Attr Default Description rrbsize:...
  • Page 372 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x140 Bit Attr Default Description...
  • Page 373Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x148 Bit Attr Default Description dcalt6:...
  • Page 374 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x14c Bit Attr Default Description...
  • Page 375Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x154 Bit Attr Default Description nmi:...
  • Page 376 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x184 Bit Attr Default Description...
  • Page 377Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x18c Bit Attr Default Description lt:...
  • Page 378 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x194 Bit Attr Default Description...
  • Page 379Integrated I/O (IIO) Configuration Registers 14.6.45 VTUNCERRSTS Intel® VT-d Uncorrectable Error Status. Type: CFG PortID: N/A Bus: 0 Device: 5Function:0...
  • Page 380 Integrated I/O (IIO) Configuration Registers 14.6.46 VTUNCERRMSK Intel® VT-d Uncorrectable Error Mask. Mask out error reporting to IIO. Bit...
  • Page 381Integrated I/O (IIO) Configuration Registers 14.6.47 VTUNCERRSEV Intel® VT-d Uncorrectable Error Severity. Type: CFG PortID: N/A Bus: 0 Device: 5Function:0...
  • Page 382 Integrated I/O (IIO) Configuration Registers 14.6.48 VTUNCERRPTR Intel® VT-d Uncorrectable Error Pointer. Type: CFG PortID: N/A Bus: 0 Device:...
  • Page 383Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x1c0 Bit Attr Default Description en_poismsg_spec_behavior:...
  • Page 384 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x1c0 Bit Attr Default Description...
  • Page 385Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x1c0 Bit Attr Default Description disable_all_allocating_flows:...
  • Page 386 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x1c0 Bit Attr Default Description...
  • Page 387Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x1c0 Bit Attr Default Description legacy_port:...
  • Page 388 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x1c0 Bit Attr Default Description...
  • Page 389Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x290 Bit Attr Default Description commandbit:...
  • Page 390 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x800 Bit Attr Default Description...
  • Page 391Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x804 Bit Attr Default Description 31:14...
  • Page 392 Integrated I/O (IIO) Configuration Registers 14.6.54 IRP[0:1]DBGRING0 Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x818, 0x820 Bit...
  • Page 393Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x830, 0x834 Bit Attr Default Description...
  • Page 394 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x830, 0x834 Bit Attr Default...
  • Page 395Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x840 Bit Attr Default Description 63:34...
  • Page 396 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x840 Bit Attr Default Description...
  • Page 397Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x850 Bit Attr Default Description ctagentry_avail_mask:...
  • Page 398 Integrated I/O (IIO) Configuration Registers 14.6.60 IRP_MISC_DFX3 Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x854 Bit Attr...
  • Page 399Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:0 Offset: 0x854 Bit Attr Default Description disable_trigger_pf_ack2_fix:...
  • Page 400 Integrated I/O (IIO) Configuration Registers Register name Offset Size NONISOCH_INV_CMP_EVTCTRL 0xa0 32 NONISOCH_INVEVTDATA 0xa4 32 VTD0_INV_COMP_EVT_ADDR 0xa8 32 VTD0_INV_COMP_EVT_UPRADDR...
  • Page 401Integrated I/O (IIO) Configuration Registers Register name Offset Size VTD1_INV_COMP_EVT_UPRADDR 0x10ac 32 VTD1_INTR_REMAP_TABLE_BASE 0x10b8 64 VTD1_FLTREC0_GPA 0x1100 64 VTD1_FLTREC0_SRC 0x1108...
  • Page 402 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x8, 0x1008 Bit Attr Default...
  • Page 403Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x10 , 0x1010 Bit Attr Default...
  • Page 404 Integrated I/O (IIO) Configuration Registers 14.7.4 VTD[0:1]_GLBCMD Intel® VT-d Global Command. Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0...
  • Page 405Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x18, 0x1018 Bit Attr Default Description...
  • Page 406 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x18, 0x1018 Bit Attr Default...
  • Page 407Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x1c, 0x101c Bit Attr Default Description...
  • Page 408 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x28 , 0x1028 Bit Attr...
  • Page 409Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x28 , 0x1028 Bit Attr Default...
  • Page 410 Integrated I/O (IIO) Configuration Registers 14.7.9 NONISOCH_FLTEVTCTRL Fault Event Control. Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset:...
  • Page 411Integrated I/O (IIO) Configuration Registers 14.7.11 VTD[0:1]_FLTEVTADDR Intel® VT-d Fault Event Address. Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0...
  • Page 412 Integrated I/O (IIO) Configuration Registers 14.7.14 VTD[0:1]_PROT_LOW_MEM_BASE Intel® VT-d Protected Memory Low Base. Type: MEM PortID: 8’h7e Bus: 0...
  • Page 413Integrated I/O (IIO) Configuration Registers 14.7.17 VTD[0:1]_PROT_HIGH_MEM_LIMIT Intel® VT-d Protected Memory High Limit. Type: MEM PortID: 8’h7e Bus: 0 Device:...
  • Page 414 Integrated I/O (IIO) Configuration Registers 14.7.20 VTD[0:1]_INV_QUEUE_ADD Intel® VT-d Invalidation Queue Address. Type: MEM PortID: 8’h7e Bus: 0 Device:...
  • Page 415Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0xa0 Bit Attr Default Description inval_nonisoch_msi_pend:...
  • Page 416 Integrated I/O (IIO) Configuration Registers 14.7.26 VTD[0:1]_INTR_REMAP_TABLE_BASE Intel® VT-d Interrupt Remapping Table Based Address. Type: MEM PortID: 8’h7e Bus:...
  • Page 417Integrated I/O (IIO) Configuration Registers 14.7.28 VTD0_FLTREC[0:7]_SRC, VTD1_FLTREC0_SRC Intel® VT-d Fault Record. Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0...
  • Page 418 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x200 , 0x1200 Bit Attr...
  • Page 419Integrated I/O (IIO) Configuration Registers Type: MEM PortID: 8’h7e Bus: 0 Device: 5Function:0 Offset: 0x208 , 0x1208 Bit Attr Default...
  • Page 420 Integrated I/O (IIO) Configuration Registers 14.8 Device 5 Function 2 Global System Control and Error Registers. Register name Offset...
  • Page 421Integrated I/O (IIO) Configuration Registers Register name Offset Size GFFERRST 0x1dc 32 GFNERRST 0x1e8 32 GNFERRST 0x1ec 32 GNNERRST 0x1f8...
  • Page 422 Integrated I/O (IIO) Configuration Registers Register name Offset Size IIOFNERRST 0x31c 32 IIONFERRST 0x320 32 IIONFERRHD_0 0x324 32 IIONFERRHD_1...
  • Page 423Integrated I/O (IIO) Configuration Registers 14.8.2 DID Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x2 Bit Attr Default...
  • Page 424 Integrated I/O (IIO) Configuration Registers 14.8.4 PCISTS Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x6 Bit Attr...
  • Page 425Integrated I/O (IIO) Configuration Registers 14.8.5 RID Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x8 Bit Attr Default...
  • Page 426 Integrated I/O (IIO) Configuration Registers 14.8.8 HDR Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0xe Bit Attr...
  • Page 427Integrated I/O (IIO) Configuration Registers 14.8.12 INTL Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x3c Bit Attr Default...
  • Page 428 Integrated I/O (IIO) Configuration Registers 14.8.16 PXPCAP Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0x42...
  • Page 429Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0x80 Bit Attr Default...
  • Page 430 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function:2 Offset: 0x8c Bit Attr Default...
  • Page 431Integrated I/O (IIO) Configuration Registers This register allows remapping of the PCIe* errors to the IIO error severity. Type: CFG...
  • Page 432 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0x9c Bit Attr...
  • Page 433Integrated I/O (IIO) Configuration Registers 14.8.23 ERRPINCTL This register provides the option to configure an error pin to either as...
  • Page 434 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0xa8 Bit Attr...
  • Page 435Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0xac Bit Attr Default...
  • Page 436 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0xb0 Bit Attr...
  • Page 437Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0xbc Bit Attr Default...
  • Page 438 Integrated I/O (IIO) Configuration Registers 14.8.30 GNERRMASK Global Non-Fatal Error Mask. This register masks the reporting of non-fatal errors...
  • Page 439Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x19c Bit Attr Default Description irp1_err_msk:...
  • Page 440 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x1a0 Bit Attr Default Description...
  • Page 441Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x1a4 Bit Attr Default Description vtd_err_msk:...
  • Page 442 Integrated I/O (IIO) Configuration Registers 14.8.33 GCERRST Global Corrected Error Status. This register indicates the corrected error reported to...
  • Page 443Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0x1a8 Bit Attr Default...
  • Page 444 Integrated I/O (IIO) Configuration Registers 14.8.35 GNERRST Global Nonfatal Error Status. This register indicates the non-fatal error reported to...
  • Page 445Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x1c0 Bit Attr Default Description irp1_err:...
  • Page 446 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x1c4 Bit Attr Default Description...
  • Page 447Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x1c8 Bit Attr Default Description mc_err_msk:...
  • Page 448 Integrated I/O (IIO) Configuration Registers 14.8.38 GSYSST Global System Event Status. This register indicates the error severity signaled by...
  • Page 449Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x1dc , 0x1e8 Bit Attr Default...
  • Page 450 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x230, 0x2b0 Bit Attr Default...
  • Page 451Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: 0x234, 0x2b4 Bit Attr Default Description...
  • Page 452 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRP0: 0x238, 0x23c IRP1: 0x2b8,...
  • Page 453Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits IRPP1:...
  • Page 454 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits...
  • Page 455Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits IRPP1:...
  • Page 456 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits...
  • Page 457Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits IRPP1:...
  • Page 458 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits...
  • Page 459Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits IRPP1:...
  • Page 460 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits...
  • Page 461Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits IRPP1:...
  • Page 462 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits...
  • Page 463Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits IRPP1:...
  • Page 464 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:2 Offset: IRPP0: 0x240, Size: 128 bits...
  • Page 465Integrated I/O (IIO) Configuration Registers 14.8.46 IRPP[0:1]NFERRST, IRPP[0:1]NNERRST IRP Protocol Non-Fatal FERR and NERR Status. The error status log indicates...
  • Page 466 Integrated I/O (IIO) Configuration Registers 14.8.47 IRPP[0:1]NFERRHD[0:3] IRP Protocol Non-Fatal FERR Header Log. Type: CFG PortID: N/A Bus: 0...
  • Page 467Integrated I/O (IIO) Configuration Registers 14.8.50 IIOERRST IIO Core Error Status. This register indicates the IIO internal core errors detected...
  • Page 468 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0x304 Bit Attr...
  • Page 469Integrated I/O (IIO) Configuration Registers 14.8.53 IIOFFERRHD_[0:3] IIO Core Fatal FERR Header. Header log stores the IIO data path header...
  • Page 470 Integrated I/O (IIO) Configuration Registers 14.8.55 IIONFERRHD_[0:3] IIO Core Non-Fatal FERR Header. Header log stores the IIO data path...
  • Page 471Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0x33c Bit Attr Default...
  • Page 472 Integrated I/O (IIO) Configuration Registers 14.8.59 MIERRCTL Miscellaneous Error Control. Type: CFG PortID: N/A Bus: 0 Device: 5 Function:...
  • Page 473Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0x38c Size: 128 bits...
  • Page 474 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5 Function: 2 Offset: 0x38c Size: 128...
  • Page 475Integrated I/O (IIO) Configuration Registers 14.8.64 MIERRCNTSEL Miscellaneous Error Count Select. Type: CFG PortID: N/A Bus: 0 Device: 5 Function:...
  • Page 476 Integrated I/O (IIO) Configuration Registers Register name Offset Size HDR 0xe 8 MBAR 0x10 32 SVID 0x2c 16 SID...
  • Page 477Integrated I/O (IIO) Configuration Registers 14.9.3 PCICMD Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0x4 Bit Attr Default...
  • Page 478 Integrated I/O (IIO) Configuration Registers 14.9.4 PCISTS Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0x6 Bit Attr...
  • Page 479Integrated I/O (IIO) Configuration Registers 14.9.5 RID Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0x8 Bit Attr Default...
  • Page 480 Integrated I/O (IIO) Configuration Registers 14.9.8 HDR Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0xe Bit Attr...
  • Page 481Integrated I/O (IIO) Configuration Registers 14.9.11 SID This value is used to identify a particular subsystem. Type: CFG PortID: N/A...
  • Page 482 Integrated I/O (IIO) Configuration Registers 14.9.15 ABAR I/OxAPIC Alternate BAR. Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset:...
  • Page 483Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0x44 Bit Attr Default Description capability_version:...
  • Page 484 Integrated I/O (IIO) Configuration Registers 14.9.19 IOAPICTETPC Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0xa0 Bit Attr...
  • Page 485Integrated I/O (IIO) Configuration Registers 14.9.20 PMCAP Power Management Capabilities. Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0xe0...
  • Page 486 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0xe4 Bit Attr Default Description...
  • Page 487Integrated I/O (IIO) Configuration Registers 14.9.23 IOADSELS1 I/OxAPIC DSELS Register 1. Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset:...
  • Page 488 Integrated I/O (IIO) Configuration Registers 14.9.25 IOINTSRC1 I/O Interrupt Source Register 1. Type: CFG PortID: N/A Bus: 0 Device:...
  • Page 489Integrated I/O (IIO) Configuration Registers 14.9.27 IOREMGPECNT Remote I/O GPE Count. Type: CFG PortID: N/A Bus: 0 Device: 5Function:4 Offset:...
  • Page 490 Integrated I/O (IIO) Configuration Registers 14.10.1 INDEX The Index Register will select which indirect register appears in the window...
  • Page 491Integrated I/O (IIO) Configuration Registers Register name Offset Size BCFG__WINDOW 0x3 32 RTL0__WINDOW 0x10 32 RTH0__WINDOW 0x11 32 RTL1__WINDOW 0x12...
  • Page 492 Integrated I/O (IIO) Configuration Registers Register name Offset Size RTL21__WINDOW 0x3a 32 RTH21__WINDOW 0x3b 32 RTL22__WINDOW 0x3c 32 RTH22__WINDOW...
  • Page 493Integrated I/O (IIO) Configuration Registers 14.10.4.3 ARBID__WINDOW This is a legacy register carried over from days of serial bus interrupt...
  • Page 494 Integrated I/O (IIO) Configuration Registers Type: MEM PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0x10, 0x12, 0x14, 0x16, 0x18,...
  • Page 495Integrated I/O (IIO) Configuration Registers Type: MEM PortID: N/A Bus: 0 Device: 5Function:4 Offset: 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a,...
  • Page 496 Integrated I/O (IIO) Configuration Registers 14.11 Device 6 Function 0, 3 and Device 7 Function 0 Device 6 Device...
  • Page 497Integrated I/O (IIO) Configuration Registers 14.11.2 DID Type: CFG PortID: N/A Bus: 0 Device: 6Function:0,3 Bus: 0 Device: 7Function:0 Offset:...
  • Page 498 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 6Function:0,3 Bus: 0 Device: 7Function:0 Offset: 0x4...
  • Page 499Integrated I/O (IIO) Configuration Registers 14.11.5 RID Type: CFG PortID: N/A Bus: 0 Device: 6Function:0,3 Bus: 0 Device: 7Function:0 Offset:...
  • Page 500 Integrated I/O (IIO) Configuration Registers 14.11.8 PLAT Type: CFG PortID: N/A Bus: 0 Device: 6Function:0,3 Bus: 0 Device: 7Function:0...
  • Page 501Integrated I/O (IIO) Configuration Registers 14.11.12 SDID Type: CFG PortID: N/A Bus: 0 Device: 6Function:0,3 Bus: 0 Device: 7Function:0 Offset:...
  • Page 502 Integrated I/O (IIO) Configuration Registers 14.11.16 MINGNT Type: CFG PortID: N/A Bus: 0 Device: 6Function:0,3 Bus: 0 Device: 7Function:0...
  • Page 503Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 6Function:0,3 Bus: 0 Device: 7Function:0 Offset: 0x40 Bit...
  • Page 504 Integrated I/O (IIO) Configuration Registers Type: CFG PortID: N/A Bus: 0 Device: 6Function:3 Bus: 0 Device: 7Function:0 Offset: 0x698...
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