Intel E7-8891 v2 CM8063601377422 Manuel D’Utilisation

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Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Channel Status 1 Register.

The Channel Status Register records the address of the last descriptor completed by 
the DMA channel. Refer to Intel® Quick Data Architecture Specification for special 
hardware requirements when software reads this register.

Descriptor Chain Address 0 Register.

This register is written by the processor to specify the first descriptor to be fetched by 
the DMA channel.

Descriptor Chain Address 1 Register.

This register is written by the processor to specify the first descriptor to be fetched by 
the DMA channel.

31:0

RO

0x0

cmpdscaddr:

This register stores the upper address bits (64B aligned) of the last descriptor 

processed. The DMA channel automatically updates this register when an 

error or successful completion occurs. For each completion, the DMA channel 

over-writes the previous value regardless of whether that value has been 

read.

31:0

RW_L

0x0

dscaddrlo:

This 64 bit field marks the address of the first descriptor to be fetched by the 

DMA channel. The least significant 6 bits must be zero for the address to be 

valid.
This register is RW if CHANCNT register is 1 otherwise this register is RO.

31:0

RW_L

0x0

dscaddrhi:

This 64 bit field marks the address of the first descriptor to be fetched by the 

DMA channel. The least significant 6 bits must be zero for the address to be 

valid.
This register is RW if CHANCNT register is 1 otherwise this register is RO.