Intel E7-8891 v2 CM8063601377422 Manuel D’Utilisation

354

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Intel

®

 Virtualization Technology (Intel

®

VT) for Directed I/O (Intel

®

VT-d), Address 

Mapping, System Management, Coherent Interface, Misc Registers.

31:1

RO

0x0

chmsipendcnst:

unused

0:0

RW_V

0x0

chmsipend:

Pending Bit (when set) indicates that the DMA engine has a pending MSI-X 

message for the DMA Channel. This bit is cleared by hardware as soon as it 

issues the MSI-X message. Note that a Pending Bit is set only if all internal 

conditions for generation of an MSIX interrupt (like the Channel Interrupt 

Disable bit being cleared, and so forth) are valid. This does not include the 

MSI-X Mask bit for the channel and the MSI-X Function Mask bit. Once set, a 

Pending Bit remains set until:
The corresponding MSI-X Mask bit and the MSI-X Function Mask bit are both 

cleared, at which time the IIO issues the pending message and clears the bit.
Pending bit is cleared when the Interrupt Disable bit in the corresponding 

'Channel Control Register (CHANCTRL)' transitions from 1b to 0b and there is 

not another interrupt pending for that channel - no MSI-X message issued.
Implementation Note: Implementations can consider an MSI message 

“issued to the system”, as soon as the message is “posted” internally in the 

device.

VID

0x0

16

DID

0x2

16

PCICMD

0x4

16

PCISTS

0x6

16

RID

0x8

8

CCR

0x9

24

CLSR

0xc

8

HDR

0xe

8

SVID

0x2c

16

SDID

0x2e

16

CAPPTR

0x34

8

INTL

0x3c

8

INTPIN

0x3d

8

PXPCAPID

0x40

8

PXPNXTPTR

0x41

8

PXPCAP

0x42

16

HDRTYPECTRL

0x80

8

MMCFG_BASE

0x84

32

MMCFG_LIMIT

0x88

32

TSEG

0xa8

64