Intel E7-8891 v2 CM8063601377422 Manuel D’Utilisation

Intel

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 Xeon

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Processor E7-2800/4800/8800 v2 Product Family

377

Datasheet Volume Two: Functional Description, February 2014

IOTLB Partitioning Control.

10:7

RW_LB

0x7

lt:

Controls the rate at which the LRU buckets should degrade.

If we are in “Cycles” mode (LRUCTRL = 0), then we will degrade LRU after 

256 * N requests where N is the value of this field.

If we are in “Request” mode (LRUCTRL = 1), then we will degrade LRU after 

16 * N cycles where N is the value of this field.

The default value of 0x7 (along with LRUCTRL=0) will give us a default 

behavior of decreasing the LRU buckets every 112 requests.

6:5

RW_LB

0x1

prefetch_control:

Queued invalidation, interrupt table read, context table reads and root table 

reads NEVER have prefetch/snarf/reuse capability. This is a general rule. 

Beyond that the Prefetch Control bits control additional behavior as shown 

below. This field controls which Intel

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VT-d reads are to be considered for 

prefetchsnarfreuse in the Intel

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QPI buffers.

00: Prefetch/snarf/reuse is turned off that is, IRP cluster never reuses the 

Intel

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VT-d read data

01: Prefetch/snarf/reuse is enabled for all leaf/non-leaf Intel

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VT-d page 

walk reads.
10: Prefetch/snarf/reuse is enabled only on leaf not non-leaf Intel

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VT-d 

page walks reads with CC.ALH bit set
11: Prefetch/snarf/reuse is enabled on ALL leaf not non-leaf Intel

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VT-d 

page walks reads regardless of the setting of the CC.ALH bit

4:4

RV

-

Reserved.

3:3

RW_LB

0x0

ignoreubitleafeviction:

Don’t use U bit in leaf entry for leaf eviction policy on untranslated DMA 

requests (AT=00b) 

2:2

RW_LB

0x0

evictnonleafat01:

Mark non-leaf entries on translation requests with AT=01 for early eviction 

1:1

RW_LB

0x0

dontevictleafat01:

Don’t mark leaf entries with U=0 on translation requests with AT=01 for 

early eviction 

0:0

RV

-

Reserved.

31:29

RV

-

Reserved.

28:27

RW

0x0

rangesel_dmi_20_22:

26:25

RW

0x0

rangesel_iou24_upper_x2: