Intel E7-8891 v2 CM8063601377422 Manuel D’Utilisation

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

397

Datasheet Volume Two: Functional Description, February 2014

28:16

RW_L

0x1fff

ctagentry_avail_mask:

This feature will mask out write cache entries in strides of 8. Each bit maps 

to the relevant write cache entries noted below:

bit0: write cache entries 7 down to 0 Note: This bit should always be set to 

'1'
bit1: write cache entries 15 down to 8
bit2: write cache entries 23 down to 16
bit3: write cache entries 31 down to 24
bit4: write cache entries 39 down to 32
bit5: write cache entries 47 down to 40
bit6: write cache entries 55 down to 48
bit7: write cache entries 63 down to 56
bit8: write cache entries 71 down to 64
bit9: write cache entries 79 down to 72
bit10: write cache entries 87 down to 80
bit11: write cache entries 95 down to 88
bit12: write cache entries 103 down to 96

where a bit is defined as:

'0': Mask out write cache entries
'1': Don’t mask out write cache entries

This mode should not be used in conjunction with rrbsize mode in CIPCTRL.

15:15

RW_L

0x0

bogus_wr_for_second_p_pf_after_wrpull:

Suppress bogus write-back if second P PF for write mergeable case comes in 

after WritePull for first P PF.

14:14

RW_L

0x0

revert_snum_to_prefetch_snum_on_flush:

Revert effective flush sequence number to prefetch/fetch issued seqnum for 

flush index
'0' : prefetch issued seqnum
'1' : fetch issued seqnum

13:13

RW_L

0x0

drop_ncs_with_error:

Drop outbound NCS messages that have errors in formatting. Do not forward 

to Switch. This is consistent with Intel Xeon processor E7-2800/4800/8800 

v2 product family Product Family behavior.

12:12

RW_L

0x0

disable_trigger_pf_ack2_fix:

Defeature mode to disable fix related to issuing second PF ack for a write 

merged entry. This is only for IRP0.

0: Enable changes
1: Disable changes

Locked by DBGBUSLCK

11:11

RV

-

Reserved:

10:10

RW_L

0x0

lterr_log_dis:

Disable error logging for LT transactions.

9:0

RV

-

Reserved: