Intel E7-4850 v2 CM8063601272906 Manuel D’Utilisation
Codes de produits
CM8063601272906
Integrated I/O (IIO) Configuration Registers
358
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.6.5
RID
14.6.6
CCR
Accesses to the CCR field are redirected to the UBox due to DWORD alignment.
8:8
RO
0x0
master_data_parity_error:
Hardwired to 0
7:7
RO
0x0
fast_back_to_back:
Not applicable to PCI Express. Hardwired to 0.
6:6
RV
-
Reserved.
5:5
RO
0x0
pci66mhz_capable:
Not applicable to PCI Express. Hardwired to 0.
4:4
RO
0x1
capabilities_list:
This bit indicates the presence of a capabilities list structure
3:3
RO
0x0
intx_status:
Hardwired to 0
2:0
RV
-
Reserved.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x8
Bit
Attr
Default
Description
7:0
RO_V
0x0
revision_id:
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID
register in any Intel Xeon processor E7-2800/4800/8800 v2 product family
Product Family function.
Implementation Note:
Read and write requests from the host to any RID register in any Intel Xeon
Read and write requests from the host to any RID register in any Intel Xeon
processor E7-2800/4800/8800 v2 product family Product Family function are
redirected to the UBox.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x6
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x9
Bit
Attr
Default
Description
23:16
RO_V
0x08
base_class:
Generic Device