Intel E7-8870 v2 CM8063601272006 Manuel D’Utilisation
Codes de produits
CM8063601272006
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
235
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
1:1
RW
0x0
senfeen:
System Error on Nonfatal Error Enable
This field enables notifying the internal IIO core error logic of
This field enables notifying the internal IIO core error logic of
occurrence of an uncorrectable nonfatal error at the port or below its
hierarchy. The internal IIO core error logic then decides if/how to
escalate the error further (pins/message etc).
1: indicates that a internal IIO core error logic notification should be
1: indicates that a internal IIO core error logic notification should be
generated if a nonfatal error (ERR_NONFATAL) is reported by any of
the devices in the hierarchy associated with and including this port.
0: No internal core error logic notification should be generated on a
0: No internal core error logic notification should be generated on a
nonfatal error (ERR_NONFATAL) reported by any of the devices in
the hierarchy associated with and including this port.
Note that generation of system notification on a PCI Express
Note that generation of system notification on a PCI Express
nonfatal error is orthogonal to generation of an MSI/INTx interrupt
for the same error. Both a system error and MSI/INTx can be
generated on a nonfatal error or software can chose one of the two.
Refer to PCI Express Base Specification, Revision 2.0 for details of
Refer to PCI Express Base Specification, Revision 2.0 for details of
how this bit is used in conjunction with other error control bits to
generate core logic notification of error events in a PCI Express port.
Note that since this register is defined only in PCIe* mode for
Note that since this register is defined only in PCIe* mode for
Device#0, this bit will read a 0 in DMI mode. So, to enable core
error logic notification on DMI mode nonfatal errors, BIOS must set
bit 34 of MISCCTRLSTS to a 1 (to override this bit) on Device#0 in
DMI mode.
0:0
RW
0x0
seceen:
System Error on Correctable Error Enable
This field controls notifying the internal IIO core error logic of the
This field controls notifying the internal IIO core error logic of the
occurrence of a correctable error in the device or below its hierarchy.
The internal core error logic of IIO then decides if/how to escalate
the error further (pins/message etc).
1: indicates that an internal core error logic notification should be
1: indicates that an internal core error logic notification should be
generated if a correctable error (ERR_COR) is reported by any of the
devices in the hierarchy associated with and including this port.
0: No internal core error logic notification should be generated on a
0: No internal core error logic notification should be generated on a
correctable error (ERR_COR) reported by any of the devices in the
hierarchy associated with and including this port.
Note that generation of system notification on a PCI Express
Note that generation of system notification on a PCI Express
correctable error is orthogonal to generation of an MSI/INTx
interrupt for the same error. Both a system error and MSI/INTx can
be generated on a correctable error or software can chose one of the
two.
Refer to PCI Express Base Specification, Revision 2.0 for details of
Refer to PCI Express Base Specification, Revision 2.0 for details of
how this bit is used in conjunction with other error control bits to
generate core logic notification of error events in a PCI Express port.
Note that since this register is defined only in PCIe* mode for
Note that since this register is defined only in PCIe* mode for
Device#0, this bit will read a 0 in DMI mode. So, to enable core
error logic notification on DMI mode correctable errors, BIOS must
set bit 33 of MISCCTRLSTS to a 1 (to override this bit) on Device#0
in DMI mode.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xac
Bit
Attr
Default
Description