Intel EXPI9404PTL Port Adapter EXPI9404PTL Manuel D’Utilisation

Increased bandwidth is very important from a networking

perspective. PCI Express provides dedicated I/O bandwidth

over a high-speed serial bus, and a network adapter using 

PCI Express I/O gets the full benefit of the higher bandwidth. 

This means that packets can travel at full wire speed and that

servers will spend far less time waiting for client responses to

complete transactions. Thus, more clients can be served faster

with shorter connect times.

In contrast, PCI and PCI-X are shared multi-drop parallel bus

structures. The more devices that share the bus, the less bus

bandwidth there is available for each device. This is illustrated

further in Figure 2, which shows the PCI-X multi-drop structure.

Also, with multiple devices on the bus, PCI-X “clocks-down” to

accommodate the speed of the slowest device on the bus.

PCI-X bus speeds and bus sharing may not have been a big

issue during the Fast Ethernet era (100 Mbps networks).

However, the migration to Gigabit Ethernet (1000 Mbps) has

strained the capacity of PCI-X by essentially consuming most

of the bandwidth resources of a server’s PCI-X bus. The same

is also true for migrating Gigabit Ethernet to the desktop,

where PCI slots have even less bandwidth for supporting

Gigabit Ethernet performance.

With a PCI bus, which is common for desktops, raw bandwidth

for a single, unshared PCI bus connection is 1 Gbps (32 bits x

33 MHz). This is inadequate for supporting full Gigabit Ethernet

capacity to the desktop (data and transfer overhead), even when

no other PCI devices are sharing the bus. For PCI-X, commonly

used for servers, the bandwidth for one slot (no bus sharing) is 8

Gbps; however, this scales down as more slots and devices are

added to the bus, as indicated in Figure 2, where multiple

devices must share the fixed amount of bus resources.

PCI Express, on the other hand, scales upward in bandwidth

with the addition of lanes. The minimum bidirectional un-

encoded bandwidth is 4 Gbps; however, it can scale up to as

high as 64 Gbps of dedicated I/O bandwidth for a 16-lane

PCI Express link.

A basic PCI Express link consists of two, low-voltage, differentially

driven pairs of signals. This basic link structure is shown in

Figure 3, where one differential signal pair is a transmit pair (Tx)

and the other is a receive pair (Rx).

The two signal pairs form a dual-simplex PCI Express channel

that is referred to as a x1 (“by 1”) lane. Because the signals are

differentially driven, PCI Express has high noise immunity due 

to line-to-ground noise cancellation in the differential signals.

Tx

Rx

Compute

r

Network

Adapter

Bandwidth diminishes as the number of slots and devices increases.

A lane consists of two 

differentially driven signal pairs between two PCI Express devices

(Device A and Device B).