Hynix HMT351R7BFR8A-H9T8 Manuel D’Utilisation
Rev. 1.2 / Dec. 2011
10
Registering Clock Driver Specifications
Capacitance Values
Input & Output Timing Requirements
Symbol
Parameter
Conditions
Min
Typ Max
Unit
C
I
Input capacitance, Data inputs
1.5
-
2.5
pF
Input capacitance, CK, CK, FBIN, FBIN
2
-
3
pF
Input capacitance, CK, CK, FBIN, FBIN
(DDR3-1600)
(DDR3-1600)
1.5
-
2.5
pF
C
IR
Input capacitance, RESET, MIRROR,
QCSEN
QCSEN
V
I
= V
DD
or GND; V
DD
= 1.5v
-
-
3
pF
Symbol
Parameter
Conditions
DDR3L-800
1066/1333
Unit
Min
Max
f
clock
Input clock frequency
Application frequency
300
670
Mhz
f
TEST
Input clock frequency
Test frequency
70
300
Mhz
t
SU
Setup time
Input valid before CK/CK
100
-
ps
t
H
Hold time
Input to remain valid after CK/CK
175
-
ps
t
PDM
Propagation delay, single-
bit switching
CK/CK to output
0.65
1.0
ns
t
DIS
Output disable time (1/2-
Clock prelaunch)
Yn/Yn to output float
0.5 tCK +
tQSK1(min)
-
ps
t
EN
Output enable time (1/2-
Clock prelaunch)
Output driving to Yn/Yn
0.5 tCK -
tQSK1(max)
-
ps